Re-synthesis for cost-efficient circuit-level timing speculation

Liu, Yuxi; Yuan, Feng; Xu, Qiang

doi:10.1145/2024724.2024760

Cited by 20 publications

(26 citation statements)

References 26 publications

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“…This method was first proposed in [2] and was preferred by later works because this mathematical approach had optimal solutions. However, compute cost grew exponentially with circuits scaling larger, and became impractical when dealing with VLSI circuits [6]. In [8] the authors proposed a graph reduction method for ILP formation in order to reduce runtime.…”

Section: Introductionmentioning

confidence: 99%

“…[3] chose locations with the max number of violated paths to maximize the benefit of buffer insertions. This method was also adopted in [5][6][7]. [5] introduced a procedure first to size down buffers, then implemented the greedy method.…”

Section: Introductionmentioning

confidence: 99%

“…[5] introduced a procedure first to size down buffers, then implemented the greedy method. While [6] introduced a procedure first to retime or relocate critical registers. This paper also did an exhaustive comparison of ILP and greedy approaches.…”

Section: Introductionmentioning

confidence: 99%

“…[7] mainly focused on a new algorithm aimed at predicting the minimum period for resilient circuits. [5][6][7] did not actually change the original algorithm of greedy heuristic proposed in [3]. Despite greedy heuristics may not give optimal solution, the area overhead is small enough to be accepted compared to ILP, and runtime is linear dependent to circuit scales [6].…”

Section: Introductionmentioning

confidence: 99%

“…[5][6][7] did not actually change the original algorithm of greedy heuristic proposed in [3]. Despite greedy heuristics may not give optimal solution, the area overhead is small enough to be accepted compared to ILP, and runtime is linear dependent to circuit scales [6]. So far greedy heuristic is still the best paper algorithm both in area reduction and runtime.…”

Section: Introductionmentioning

confidence: 99%

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An effectiveness-oriented greedy heuristic for padding short paths in ultra-low supply voltage designs

Meng

Chen

et al. 2018

IEICE Electron. Express

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Abstract:Among prior short paths padding algorithms, greedy heuristic based on the number of short paths had been proven to be area saving and fast. For ultra-low supply multi-voltage designs, however, delay buffers explode due to improper padding locations caused by unconsidered delay variations. To overcome this problem, we propose a new evaluation function "effectiveness" for greedy heuristic, to characterize the benefit of buffer insertion, thereby to optimize the allocation of padding delay and reduce buffer overhead. An improved algorithm to dynamically update slacks during delay assignment stage is also introduced. Experimental results show average area reduction of 91.6% compared to the prior method.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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An effectiveness-oriented greedy heuristic for padding short paths in ultra-low supply voltage designs

Meng

Chen

et al. 2018

IEICE Electron. Express

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A Dedicated Greedy Short Path Padding Solution Method for Error Resilient Circuit Designs

Chen

Xiang

et al. 2020

IEEE Access

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Resilient circuits represent promising approaches for improving both circuit performance and tolerance for dynamic variations. However, the short path padding problem becomes severe during the implementation, resulting in significant area overhead and even frequency degradation, which might nullify the benefits of resilience. The present work addresses this issue by proposing a progressive resilient design methodology, including a clock period prediction method that can accurately access the minimum clock period possible in an early stage and a short path padding method, based on the greedy heuristic algorithm to reduce both the total padding delay and the runtime. The runtime for the padding stage is further minimized by introducing an accelerated padding method that decreases the number of point visits required during the greedy padding process. The proposed methodology is applied to several benchmark circuits, decreasing averagely 26.1% in the total number of padding buffers and 38.1% in the runtime, compared to a present state of the art methodology. Thus, this proposal not only avoids iterations of padding assignments by early period prediction, but also is a feasible and effective short path padding methodology for resilient circuits.

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