Correlation of trap generation to charge-to-breakdown (Q/sub bd/): a physical-damage model of dielectric breakdown

Apte, Pushkar P.; Saraswat, Krishna C.

doi:10.1109/16.310111

Cited by 101 publications

(41 citation statements)

References 27 publications

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“…Beginning in the early 1990s, it was reported that in a large variety of oxide thickness stressed over a wide range of voltages, the charge-to-breakdown is inversely related to the initial rate of defect generation for most stress conditions [19], [88], [101]- [103]. Extending this to thinner samples, the thickness dependence of oxide breakdown was explained as resulting from a thickness-dependent number of defects required to trigger breakdown [24].…”

Section: The Critical Defect Densitymentioning

confidence: 99%

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Stathis

2001

IEEE Trans. Device Mater. Relib.

163

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Abstract-The microelectronics industry owes its considerable success largely to the existence of the thermal oxide of silicon. However, recently there is concern that the reliability of ultra-thin dielectrics will limit further scaling to slightly thinner than 2 nm. This paper will review the physics and statistics of dielectric wearout and breakdown in ultrathin SiO 2 -based gate dielectrics. Electrons or holes tunneling through the gate oxide generate defects until a critical density is reached and the oxide breaks down. The critical defect density is explained by the formation of a percolation path of defects across the oxide. Only 1% of these paths ultimately lead to destructive breakdown, and the microscopic nature of these defects is not known. The rate of defect generation decreases approximately exponentially with supply voltage, below a threshold voltage of about 5 V for hot electron-induced hydrogen release. However, the tunnel current also increases exponentially with decreasing oxide thickness, leading to a decreasing time-to-breakdown and a diminishing margin for reliability as device dimensions are scaled. Estimating the reliability of the dielectric requires an extrapolation from the measurement conditions (e.g., higher voltage) to operation conditions. Because of the diminished reliability margin, it has become imperative to try to reduce the error in this extrapolation.Long-term ( 1 year) stress experiments are now being used to measure the wearout and breakdown of ultrathin ( 2 nm) dielectric films as close as possible to operating conditions. These measurements have revealed the details of the voltage dependence of the defect generation rate and critical defect density, allowing better modeling of the voltage dependence of the time-to-breakdown. Such measurements are used to guide the technology development prior to the manufacturing stage. We then discuss the nature of the electrical conduction through a breakdown spot and the effect of the oxide breakdown on device and circuit performance. In some cases, an oxide breakdown does not lead to immediate circuit failure, so more research is needed in order to develop a quantitative methodology for predicting the reliability of circuits.

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Section: The Critical Defect Densitymentioning

confidence: 99%

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Stathis

2001

IEEE Trans. Device Mater. Relib.

163

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“…Apte investigated oxide degradation by a systematic study of five technologically relevant parameters, namely stresscurrent density, oxide thickness, stress temperature, charge injection polarity and nitridation of pure oxide. 7 For the five parameters, a strong correlation has been observed between oxide degradation and the generation of new traps. Trap generation acts as an excellent monitor of the dielectric degradation that leads to the eventual breakdown of the oxide.…”

Section: Introductionmentioning

confidence: 91%

A new method of thin gate SiO₂ reliability characterization

Liu

2002

Surface & Interface Analysis

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Time-dependent dielectric breakdown (TDDB) of thin gate oxides is an important reliability issue of MOS integrated circuits. Breakdown characteristics of thin gate oxides are measured under constant voltage stress (CVS). Effects of the gate voltage and gate oxide area on charge to breakdown Q bd are discussed. The experimental results show that Q bd is not a constant; Q bd depends on both the gate oxide area and stress voltage and cannot act as the breakdown criterion over a wider stress range. Based on experimental results, a novel empirical power law is proposed to characterize thin gate oxide reliability and the correlated parameters are fitted. The empirical power law has been used in extrapolations to obtain Q bd for an arbitrary oxide area and gate voltage. Extrapolated results are in good agreement with those measured at constant voltage, so it is a useful tool for predicting thin gate oxide reliability.

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“…Although it is generally accepted that high temperature degrades oxide breakdown characteristics due to increased interaction between tunneling electrons and oxide lattice, 4 enhancing electron trap generation rate, 5 thereby causing enhanced tunneling-induced trap generation 6 and reduced immunity to electrical stress, 7 however, the exact mechanism involves remains unclear. Many recent studies indeed confirmed that wafer temperature during processing is a crucial parameter for process-induced oxide degradation, and gate oxide is more susceptible to charging damage at elevated temperature.…”

mentioning

confidence: 99%

Temperature-accelerated dielectric breakdown in ultrathin gate oxides

Chen

Chang

Chien

et al. 1999

Applied Physics Letters

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Temperature-accelerated effects on dielectric breakdown of ultrathin gate oxide with thickness ranging from 8.7 to 2.5 nm are investigated and analyzed. Although superior reliability for ultrathin gate oxide at room temperature has been reported in recent literatures, a strong temperature-accelerated degradation of oxide reliability is observed in this study. Experimental results show that both charge-to-breakdown (Qbd) and breakdown field (Ebd) characteristics are greatly aggravated for ultrathin oxide at elevated temperature. The Arrhenius plot also confirms that the activation energies of Qbd and Ebd increase significantly as oxide thickness decreases, explaining the higher sensitivity to temperature for thinner oxides.

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Correlation of trap generation to charge-to-breakdown (Q/sub bd/): a physical-damage model of dielectric breakdown

Cited by 101 publications

References 27 publications

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

A new method of thin gate SiO₂ reliability characterization

Temperature-accelerated dielectric breakdown in ultrathin gate oxides

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Correlation of trap generation to charge-to-breakdown (Q/sub bd/): a physical-damage model of dielectric breakdown

Cited by 101 publications

References 27 publications

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

A new method of thin gate SiO2 reliability characterization

Temperature-accelerated dielectric breakdown in ultrathin gate oxides

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Product

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A new method of thin gate SiO₂ reliability characterization