Temperature-accelerated dielectric breakdown in ultrathin gate oxides

Abstract

Temperature-accelerated effects on dielectric breakdown of ultrathin gate oxide with thickness ranging from 8.7 to 2.5 nm are investigated and analyzed. Although superior reliability for ultrathin gate oxide at room temperature has been reported in recent literatures, a strong temperature-accelerated degradation of oxide reliability is observed in this study. Experimental results show that both charge-to-breakdown (Qbd) and breakdown field (Ebd) characteristics are greatly aggravated for ultrathin oxide at elevated temperature. The Arrhenius plot also confirms that the activation energies of Qbd and Ebd increase significantly as oxide thickness decreases, explaining the higher sensitivity to temperature for thinner oxides.

Oxide Wearout, Breakdown, and Reliability

“…The voltage acceleration seems to fit the breakdown data better for very thin oxides with low applied voltages and when corrections are made for the internal oxide field. There has been much effort devoted to determining the temperature acceleration factors, particularly since low-voltage stresses are often performed at elevated temperatures in order to reduce the time-to-breakdown [62,166,217,271,[876][877][878][879][880]. It has been found that, due to the complex time dependence of wearout, breakdowns have non-Arrhenius dependencies [581,714,881,882].…”

A high density FinFET one-time programmable cell with new intra-fin cell isolation for advanced system on chip applications

“…However, for general applications, in order to protect the peripheral circuits from high voltage stresses in a program, the pulses biased at V WL = 1.2 V, V SL = 4 V with 20 µs are selected as the typical condition for the following characterizations. In addition to a different operation voltage, a higher ambient temperature also accelerates the high-κ gate dielectric breakdown [29][30][31] by a larger thermal leakage with the activation energy of 0.6 eV. Figure 6 shows the variation of program characteristics at different temperatures; the higher background temperature shortens the program time under the same operation voltage.…”

A new 28 nm high-k metal gate CMOS logic one-time programmable memory cell

“…6 indicates the temperature effect on breakdown characteristic of gate dielectric. [28][29][30] For high-k gate stack, the temperature dependence of time-dependent dielectric breakdown (TDDB) lifetime mainly depends on the stress-induced leakage current (SILC) and the defect creation and distribution. At elevated temperature, defect creation will be enhanced.…”