A new two-transistor embedded resistive RAM (RRAM) cell with fully Taiwan Semiconductor Manufacturing Company 28-nm CMOS logic compatible process is reported. The new 28-nm logic compatible RRAM cell consists of two logic standard high-k metal gate (HKMG) CMOS transistors with a composite resistive gate dielectric of TiN/HfO 2 /SiO 2 /Si as a resistive memory storage node. Using one of the transistor gates as a source line in RRAM SET/RESET operation, the resistive memory states can be efficiently read and sensed by selecting the other transistor gate and its corresponding bitline. Therefore, the new 2T embedded RRAM cell has realized a logic nonvolatile memory (NVM) solution with cost effective, and fully compatible with 28-nm HKMG CMOS logic platforms. Besides, through adapting the existing high-K gate dielectric in the RRAM cell, the embedded memory cell does not need any additional deposition of resistive film or extra process steps and it will be very scalable and compatible with the fast progress of CMOS technologies in embedded NVM applications. Furthermore, its low voltage requirement makes this cell conveniently fit in logic intellectual properties and circuits for local data storages or level trimming devices on system-on-chip logic NVM products.Index Terms-28-nm high-k metal gate (HKMG) CMOS logic process, embedded resistive RAM (RRAM), nonvolatile memory.
This work presents a high density high-k metal gate (HKMG) one-time programmable (OTP) cell. Without additional processes and steps, this OTP cell is fully compatible to 28 nm HKMG CMOS process. The OTP cell adopts high-k dielectric breakdown as programming mechanism to obtain more than 105 times of on/off read window. Moreover, it features low power and fast program speed by 4.5 V program voltage in 100 µs. In addition to the ultrasmall cell area of 0.0425 µm2, the superior performance of disturb immunities and data retention further support the new logic OTP cell to be a very promising solution in advanced logic non-volatile memory (NVM) applications.
A high density high-k gate dielectric breakdown OTP cell with a self-aligned twin-gate isolation in pure 28nm HKMG process is demonstrated. With a merged spacer isolation formed by two tiny metal gates, the OTP cells can be well isolated with an ultra small cell size of 0.0441 Ilm2 in pure 28nm CMOS logic process. The Tw in-Gate OTP memory adopts low voltage high-k dielectric breakdown mechanism to obtain 104 times of On/Off ratio by a low program voltage of 4V in 20lls. A tiny and excellent Twin-Gate isolation with wide program and temperature margins has been successfully achieved in this OTP cell. Superior disturbs immunity and data retention further support the new logic OTP cell to be a promising solution in advanced logic NVM applications.
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