Copper Precipitation at the Silicon-Silicon-Dioxide Interface: Role of Oxygen

A much higher leakage current, a lower breakdown effective field, a poorer charge-to-breakdown, and worse stress-induced leakage current are observed in ultrathin 30 Å oxides even at a low Cu contamination of 10 ppb. The strong degradation of the ultrathin gate oxide integrity can be explained by the tunneling barrier lowering and the increased interface trap tunneling due to the presence of Cu in the oxide and at the oxide-Si interface.Cu contamination 1-7 has attracted much attention in advanced high-speed complementary metal oxide semiconductors ͑CMOS͒ circuits using Cu metallization. The Cu contamination, which may come from either the front surface Cu interconnects or the back-side surface contaminated by the Cu process, may precipitate at the Si/SiO 2 interface 5,7,8 or form a silicide by a reaction with Si. The Cu contamination can degrade metal oxide field effect transistor's ͑MOSFETs͒ performance by increasing the leakage current at the source-drain junction, shifting the threshold voltage, and increasing the subthreshold swing. 8,9 The Cu contamination may also degrade the gate oxide integrity by reducing the breakdown electric field at high contamination levels, 2 but has little effect on the gate area oxide breakdown at low contamination levels. 1 However, most of the reported Cu contamination studies are focused on relatively thick oxides. In this paper, we have examined the gate oxide integrity 10-12 of Cu-contaminated ultrathin ϳ30 Å oxides used for an 0.18 m generation. In contrast to previous reports on thick oxides, we have found severe degradation of the gate oxide integrity for these ultrathin ϳ30 Å oxides. Compared with the control sample, the contaminated oxides show higher direct and Fowler-Nordheim ͑F-N͒ tunneling currents, lower breakdown electric field, poorer charge-to-breakdown distribution (Q BD ), and worse stress-induced leakage current ͑SILC͒, even at a low Cu contamination level of 10 ppb. This is probably due to the presence of Cu within both the oxide and the Si-oxide interface, which effectively lowers the tunneling barrier and increases the SILC. ExperimentalStandard 4 in. p-type Si ͑100͒ wafers with a typical resistivity of ϳ10 ⍀ cm were used in this study. The preoxidation cleaning of the wafers was performed by a modified RCA clean, followed by HF dipping, and spin drying. Device isolation was formed by growing and patterning the 3000 Å thick field oxide. Then the ϳ30 Å gate oxide was grown at 900°C in dry oxygen diluted with nitrogen. The oxide thickness was measured by ellipsometry and high frequency C-V measurements under accumulation. The gate electrode was formed by depositing a 3000 Å poly-Si with subsequent phosphorus doping by POCl 3 . The standard aluminum contact was formed by thermal evaporation, and MOS capacitors of 100 ϫ 100 m were fabricated. The Cu contamination was introduced by dipping the devices for 1 min into a CuSO 4 solution with a concentration of 10 ppb or 10 ppm, and the contaminated wafer was then annealed at 400°C in a nitrogen gas ambient. Figur...

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confidence: 99%

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confidence: 99%

The Strong Degradation of 30 Å Gate Oxide Integrity Contaminated by Copper

Chen

Chan

Pan

et al. 2001

“…Copper (Cu) contamination [1][2][3][4][5][6][7][8] in Si complementary metal-oxidesemiconductor (CMOS) based devices has attracted much attention recently, because Cu may come from either the front-end or backend process. It has been reported that Cu can affect the threshold voltage of MOS transistors, 1 and form precipitate or silicide at the Si/SiO 2 interface.…”

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confidence: 99%

“…It has been reported that Cu can affect the threshold voltage of MOS transistors, 1 and form precipitate or silicide at the Si/SiO 2 interface. 5,8 The oxide breakdown voltage is reduced under a condition of high contamination levels, 2,5,8 but, for slight contamination, significant electrical degradation only occurs at the field overlap edge 3 with little effect on the area gate oxide breakdown. 4,6,7 While most previous works have primarily focused on the front-end preoxidation Cu contamination, Cu contamination introduced by Cu interconnection processes, such as Cu electroplating and chemical mechanical polishing (CMP) becomes an important concern.…”

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confidence: 99%

The Effect of Copper on Gate Oxide Integrity

Chin

Pan

2000

We have studied the effect of copper contamination after the front-end metal-oxide-semiconductor capacitor fabrication on gate oxide integrity. The significant effect of Cu contamination on the pretunneling current, in combination with insensitive dependence of the Fowler-Nordheim tunneling current, oxide charge density, and breakdown field on the Cu concentration, suggests that the current leakage mechanism may be due to neutral traps generated by Cu inside oxide. In addition to pretunneling oxide leakage, a small amount of Cu contamination increases the interface trap density that may degrade the device performance.

“…However, Cu diffusion into low-and front-end metal-oxide semiconductor field effect transistors ͑MOSFETs͒ is an important issue. [1][2][3][4][5][6][7][8][9][10][11][12] The Cu contamination from back-end Cu interconnects or the back-side wafer surface contaminated by Cu accumulates at the Si/SiO 2 interface [6][7][8] or reacts with Si to form silicide. The precipitate Cu at the oxide interface increases the subthreshold swing of MOSFETs, 7,9 shifts the threshold voltage, and degrades the gate leakage current.…”

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confidence: 99%

The Copper Contamination Effect of Al[sub 2]O[sub 3] Gate Dielectric on Si

Liao

Cheng

et al. 2004

We have studied the Cu contamination effect on 4.2 nm thick Al 2 O 3 metal-oxide semiconductor ͑MOS͒ capacitors with an equivalent-oxide thickness ͑EOT͒ of 1.9 nm. In contrast to the large degradation of gate oxide integrity of control 3.0 nm SiO 2 MOS capacitors contaminated by Cu, the 1.9 nm EOT Al 2 O 3 MOS devices have good Cu contamination resistance with only small degradation of gate dielectric leakage current, charge-to-breakdown, and stress-induced leakage current. This strong Cu contamination resistance is similar to oxynitride ͑with high nitrogen content͒, but the Al 2 O 3 gate dielectric has the advantage of higher value and lower gate dielectric leakage current.To reduce the circuit's RC delay from back-end metal lines and parasitic capacitors, Cu and low-dielectric are required. However, Cu diffusion into low-and front-end metal-oxide semiconductor field effect transistors ͑MOSFETs͒ is an important issue. 1-12 The Cu contamination from back-end Cu interconnects or the back-side wafer surface contaminated by Cu accumulates at the Si/SiO 2 interface 6-8 or reacts with Si to form silicide. The precipitate Cu at the oxide interface increases the subthreshold swing of MOSFETs, 7,9 shifts the threshold voltage, and degrades the gate leakage current. [10][11][12] The Cu silicide also increases the unwanted leakage current in the source-drain junction. To reduce Cu diffusion during back-end thermal cycling, a barrier metal under Cu and thick SiN between each intermetal layer ͑IML͒ dielectric are usually added. However, the added SiN of typically 50 nm has a large -value of 7.5 and degrades the total of combined IML dielectric and SiN. The increasing effective is unfavorable because it increases the circuit's back-end resistance-capacitance ͑RC͒ delay. In this paper, we have studied the Cu contamination effect in highAl 2 O 3 gate dielectric 13-16 with small equivalent-oxide thickness ͑EOT͒ of 1.9 nm, where the high-gate dielectric is important for continuously scaling down the nanometer-scale MOSFET. In contrast to the large degradation of gate oxide integrity in 3.0 nm thermal SiO 2 , the smaller 1.9 nm EOT Al 2 O 3 gate dielectric shows much better resistance to Cu contamination-related degradation on gate dielectric leakage current, charge-to-breakdown (Q BD ), and stress-induced leakage current ͑SILC͒. Therefore, the high-gate dielectric with Al 2 O 3 ternary compound such as HfAlO or LaAlO 3 should have this additional advantage besides the high-value. This is the first study of Cu diffusion in high-Al 2 O 3 . ExperimentalStandard 4 in., p-type Si͑100͒ wafers with a typical resistivity of ϳ10 ⍀-cm were used in this study. After standard cleaning, the device active region was formed by thick field oxide and patterning. Then the ϳ4.2 nm Al 2 O 3 was formed by physical-vapor deposition from an Al 2 O 3 sputter source, oxidation at 400°C under O 2 ambient for 5 min, and annealed at N 2 ambient for 25 min. From the capacitance-voltage ͑C-V͒ measurement, a value of 8.5 and EOT of 1.9 nm were obtained. Then t...