Control of Two Types of Dielectric Relaxation Current for Ta₂O₅Metal-Insulator-Metal Capacitors

Abstract

Positive pressure infusion of Y 2 O 3 :Eu 3+ particles 8-12 nm in size was carried out in 75 cm 3 samples of 0.6% agarose gels that have internal mass transport properties similar to those of in vivo mammalian brain tissue. The purpose of the study was to investigate the nature of the porous-like structure of the gels at distance scales of the order of ≈10 nm. Fluorescence of the particles under UV excitation was used to observe their time-dependent distribution pattern, with the result that the convection-enhanced flow provided by the infusion process caused the particles to permeate the gel's interstitial structure, thus revealing a porosity scale size commensurate with that of the particle size.

Dielectric relaxation study of hydrogen exposure as a source of two-level systems in Al2O3

“…Examples of these include threshold voltage shifts in metal-oxide-semiconductor field-effect transistors (MOSFETs) [9], "charge loss" in dynamic random access memory (DRAM) [10], and errors in analog-to-digital converters (ADCs) [11]. The impact of TLSs on electronics thus appears truly widespread.…”

A semiclassical model of dielectric relaxation in glasses

“…The earliest suggestion was by Curie, who observed in his original study 3 that the dielectric relaxation of porcelain increased with water content. However, even though a distribution of relaxation rates can yield the required 1 / t n time dependence, this does not prove that such a distribution actually exists, or what the relaxation rates correspond to physically, and this has cast a lingering doubt on the validity of the hypothesis ͑see, for example, the article by Kiyotoshi et al 14 from 2003͒. Jonscher 26 has reviewed a number of other hypotheses, and of these, perhaps the most widely held belief is that dielectric relaxation represents the summation of many independent relaxation processes, each of which has an exponential dependence on time, exp͑−t / ͒.…”

Performance Improvement of Capacitorless Dynamic Random Access Memory Cell with Band-Gap Engineered Source and Drain

“…As dynamic random access memory (DRAM) Cell technology scales into the sub 50 nm regime, the traditional onetransistor and one-capacitor (1T/1C) DRAM cell faces some challenges, such as the requirement for stack/trench capacitor or novel dielectric materials, which may lead to process complexity and reliability issues. [1][2][3][4][5] Recently, a process compatible capacitorless DRAM cell utilizing floating body as a charge storage element, has been proposed and attracted much attention. [6][7][8][9][10][11][12][13][14][15] However, with the cell size scaling down, the sensing current and retention time of floating body cell (FBC) are decreased, due to the physical limit of body potential shift (ÁV BS ) and drain induced barrier lowering (DIBL) effect.…”