Content-addressable memory core cells A survey

Schultz, K.J.

doi:10.1016/s0167-9260(97)00021-7

Cited by 48 publications

(9 citation statements)

References 14 publications

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“…Associative memory (AM) is a sub-domain of artificial neural networks, which utilises the benefits of content-addressable memory (CAM) [10] in microcomputers. The AM concept was originally developed in an effort to utilise the power and speed of existing computer systems for solving large-scale and computationally intensive problems by simulating biological neurosystems.…”

Section: Related Workmentioning

confidence: 99%

Holographic Graph Neuron: A Bioinspired Architecture for Pattern Processing

Kleyko

Osipov

Senior

et al. 2017

IEEE Trans. Neural Netw. Learning Syst.

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Abstract-This article proposes the use of Vector Symbolic Architectures for implementing Hierarchical Graph Neuron, an architecture for memorizing patterns of generic sensor stimuli. The adoption of a Vector Symbolic representation ensures a one-layered design for the approach, while maintaining the previously reported properties and performance characteristics of Hierarchical Graph Neuron, and also improving the noise resistance of the architecture. The proposed architecture enables a linear (with respect to the number of stored entries) time search for an arbitrary sub-pattern.

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Section: Related Workmentioning

confidence: 99%

Holographic Graph Neuron: A Bioinspired Architecture for Pattern Processing

Kleyko

Osipov

Senior

et al. 2017

IEEE Trans. Neural Netw. Learning Syst.

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“…There have been many attempts to reduce the transistor count and resulting area for the CAM XOR block. A comprehensive review of different varieties of CAM cells, which can be equally applicable to TCAM cells, was presented in [15]. In [16], the authors found the TCAM cell shown in Fig.…”

Section: Conventional Tcam Arraysmentioning

confidence: 99%

Low-power Ternary Content Addressable Memory (TCAM) array for network applications

Patwary

Geuskens

2009

2009 International Conference on Communications, Circuits and Systems

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A low-power Ternary Content Addressable Memory (TCAM) array using 16-transistor core memory cells is presented for network applications where the contents of the array are not updated very frequently. In the proposed array, the read and search operations are performed by the same circuit blocks resulting in the reduction of device count and area compared to conventional TCAM arrays. Total width of the devices in the proposed TCAM cell is 18% less compared to the currently available area efficient design of TCAM cells. Simulations results using a 32 nm process technology show that under the same robustness against noise, the proposed array dissipates 12% less leakage power with minimal impact on frequency of operation when compared to known design of low-power TCAM arrays.

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“…First, we introduce an initial cache with no dedicated power optimization techniques. The initial cache design is a 16 kB, uses nine-transistor NOR-type match line CAM cells [15] and the 6T SRAM cells, for the tag array and the data array circuits, respectively. A single-ended sense TABLE I ACTIVE POWER REDUCTION TECHNIQUES TABLE II LEAKAGE POWER REDUCTION TECHNIQUES amplifier was used for match-line signal sensing in the tag array and a cross-coupled inverter latch was used for read data sensing in the data array.…”

Section: Low Power Baseline Cachementioning

confidence: 99%

Data Memory Subsystem Resilient to Process Variations

Bennaser

Guo

Moritz

2008

IEEE Trans. VLSI Syst.

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As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance of processors by making the latency of circuits less predictable and thus requiring conservative design approaches. In this paper, we use Monte Carlo simulations in addition to worst-case circuit analysis to establish the overall delay due to process variations in a data cache sub-system under both typical and worst-case conditions. The distribution of the cache critical-path-delay in the typical scenario was determined by performing Monte Carlo simulations at different supply voltages, threshold voltages, and transistor lengths on a complete cache design. In addition to establishing the delay variation, we present an adaptive variable-cycle-latency cache architecture that mitigates the impact of process variations on access latency by closely following the typical latency behavior rather than assuming a conservative worst-case design-point. Simulation results show that our adaptive data cache can achieve a 9% to 31% performance improvement in a superscalar processor, on the SPEC2000 applications studied, compared to a conventional design. The area overhead for the additional circuits of the adaptive technique has less than 1% of the total cache area. Additional performance improvement potential exists in processors where the data cache access is on the critical path, by allowing a more aggressive clock rate.Index Terms-CMOS memory integrated circuits, memory architecture, process variations.

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Content-addressable memory core cells A survey

Cited by 48 publications

References 14 publications

Holographic Graph Neuron: A Bioinspired Architecture for Pattern Processing

Holographic Graph Neuron: A Bioinspired Architecture for Pattern Processing

Low-power Ternary Content Addressable Memory (TCAM) array for network applications

Data Memory Subsystem Resilient to Process Variations

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