Constrained Symbolic Simulation with Mathematica and ACL2

Sammane, Ghiath Al; Toma, Diana; Schmaltz, Julien; Ostier, P.; Borrione, D.

doi:10.1007/978-3-540-39724-3_14

Cited by 3 publications

(1 citation statement)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…TheoSim is based on Constrained Symbolic Simulation [17]. It provides a VHDL compiler, an event driven symbolic simulator written in Mathematica and the automatic generation of functional formalizations and theorems submitted to the ACL2 theorem prover.…”

Section: Principle and Structurementioning

confidence: 99%

TheoSim

Sammane

Schmaltz

Toma

et al. 2004

Proceedings of the 17th Symposium on Integrated Circuits and System Design

View full text Add to dashboard Cite

TheoSim is a symbolic verification tool that fills the gap between the simulation of test cases, and the use of theorem provers, for the validation of initial specifications, and the exploration of the very first design steps of digital integrated systems. The principles of Theosim are presented, followed by its application to the verification of the first design step of a state-of-the-art network on chip architecture.

show abstract

Section: Principle and Structurementioning

confidence: 99%

TheoSim

Sammane

Schmaltz

Toma

et al. 2004

Proceedings of the 17th Symposium on Integrated Circuits and System Design

View full text Add to dashboard Cite

show abstract

Design of a proven correct SHA circuit

Toma

Pérez

Borrione

et al. 2004

International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.

View full text Add to dashboard Cite

show abstract

Formal design and verification of on chip networking

Sammane¹,

Schmaltz²,

Borrione³

Proceedings. 2004 International Conference on Information and Communication Technologies: From Theory to Applications, 2004.

View full text Add to dashboard Cite

ISBN: 0780384822In this paper the formal design of networks and verification of on chip networking is presented in this paper. Basic octagon architecture with bidirectional links is demonstrated for this analysis. An octagon packet is the data that must be carried from the source node to the destination node. A network on chip model, written in a standard design language (VHDL) and the behavior is simulated on traffic hypotheses. An assertion-based verification in TheoSim is used to prove the expression satisfies the properties. The method is supported by a combination of simulation and symbolic reasoning engines that bridges the gap between specification and implementation debugging

show abstract

Constrained Symbolic Simulation with Mathematica and ACL2

Abstract: Abstract. We use symbolic simulation for the verification of high level circuit specifications. We combine Mathematica for algebraic computation and ACL2 for branching decision to increase the efficiency of the method.

Cited by 3 publications

References 3 publications

TheoSim

TheoSim

Design of a proven correct SHA circuit

Formal design and verification of on chip networking

Contact Info

Product

Resources

About