Proceedings of the 17th Symposium on Integrated Circuits and System Design 2004
DOI: 10.1145/1016568.1016591
|View full text |Cite
|
Sign up to set email alerts
|

TheoSim

Abstract: TheoSim is a symbolic verification tool that fills the gap between the simulation of test cases, and the use of theorem provers, for the validation of initial specifications, and the exploration of the very first design steps of digital integrated systems. The principles of Theosim are presented, followed by its application to the verification of the first design step of a state-of-the-art network on chip architecture.

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

0
0
0

Year Published

2008
2008
2010
2010

Publication Types

Select...
3
1

Relationship

0
4

Authors

Journals

citations
Cited by 4 publications
references
References 21 publications
0
0
0
Order By: Relevance