Mixed-Signal extensions to VHDL, Verilog, and SystemC languages have been developed in order to provide a unifying environment for the modeling and verification of Analog and Mixed Signal (AMS) designs at different levels of abstraction. In this paper, we model the behavior of a set of benchmark designs in VHDL-AMS, Verilog-AMS and SystemC-AMS and compare the simulation performance with HSPICE. The various experimental results observed for the benchmark circuits show the superiority of VHDL-AMS and Verilog-AMS against SystemC-AMS and HSPICE in terms of simulation runtimes at lower level of abstraction.
In this paper, we are interested in defining a platform for high level model checking using Multiway Decision Graphs (MDGs) within High Order Logic. The platform is based on the logical formulation of an MDG as a Directed Formulae (DF). The DF is defined in the HOL theorem prover where the many sorted first-order logic is characterized as a HOL built-in data type. Then, the HOL inference rules are defined to check the well-formedness conditions of any directed formula. Based on this formalization, the MDGs operations are defined as inference rules and consistency and well-formedness proof of each operation is provided. Finally, some experimental results are presented to show the performance of the MDG-HOL platform. The obtained results show that this platform offers a considerable gain in terms of automation without sacrificing CPU time and memory usage. Forum on Specification and Design Languages 2008 978-1-4244-2265-4/08/$25.00
In this paper, all the necessary infrastructure is provided to define a state exploration approach within the HOL theorem prover. While related work has tackled the same problem by representing primitive Binary Decision Diagram (BDD) operations as inference rules added to the core of the theorem prover, the presented approach is based on the Multiway Decision Graphs (MDGs). MDG generalizes BDD to represent and manipulate a subset of first-order logic formulae. Considering MDG instead of BDD will raise the abstraction level of what can be verified using states exploration within a theorem prover. A canonic MDGs is defined in HOL as well-formed directed formulae. Then, the basic MDG operations is formalized following a deep embedding approach and the correctness proof for each operation is derived. Finally, the reachability analysis is implemented as a tactic that uses the MDG theory within HOL.
Analog and mixed signal (AMS) circuits play an important role in today's System on Chip design. They pose, however, many challenges in the verification of the overall system due to their complex behavior. Among many developed verification techniques, runtime verification has been shown to be effective by experimenting finite executions instead of going through the whole state space. In this paper, we present a methodology for the specification and verification of AMS designs using online monitoring at runtime based on the notion of System of Recurrence Equations (SREs). We implement the proposed methodology in a C language based tool, called C-SRE, and utilize it to verify several properties of a PLL design. We compare our proposed online monitoring techniques with the offline approach. Finally, we apply the proposed methodology to monitor the jitter noise associated with a voltage controlled oscillator.
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