Multiplication is one of the most basic arithmetic operations. It is used in digital applications, central processing units, and digital signal processors. In most systems, the multiplier lies within the critical path and hence, due to probability and reliability issues, the power consumption of the multiplier has become very important. Moreover, as chips shrink and their power densities increase, power is becoming a major concern for chip designers. The ever increasing demand for portable applications with their limited battery lifetime indicates that power considerations should be a center stone in today's designs and the future's designs. Thus, all this has motivated us to provide a novel circuit design technique for a low power multiplier without compromising the multiplier's speed.This paper presents a new power aware multiplier design based on Wallace tree structure. A new algorithm is proposed using high-order counters to meet the power constraints imposed by mobility and shrinking technology. Commonly used multipliers of widths 8, 16, and 32 bits are designed based on the proposed algorithm. The new approach has succeeded in reducing the total number of gates used in the multiplier tree. Simulations on Altera's Quartus-II FPGA simulator showed that the design achieves an average of 18.6% power reduction compared to the original Wallace tree. The design performs even better as the multiplier's size increases, achieving a 5% gate count reduction, a 26.5% power reduction, and a 23.9% better power-delay product in 32-bit multipliers.
Security of sensitive data exchanged between devices is essential. Low-resource devices (LRDs), designed for constrained environments, are increasingly becoming ubiquitous. Lightweight block ciphers provide confidentiality for LRDs by balancing the required security with minimal resource overhead. SIMON is a lightweight block cipher targeted for hardware implementations. The objective of this research is to implement, optimize, and model SIMON cipher design for LRDs, with an emphasis on energy and power, which are critical metrics for LRDs. Various implementations use field-programmable gate array (FPGA) technology. Two types of design implementations are examined: scalar and pipelined. Results show that scalar implementations require 39% less resources and 45% less power consumption. The pipelined implementations demonstrate 12 times the throughput and consume 31% less energy. Moreover, the most energy-efficient and optimum design is a two-round pipelined implementation, which consumes 31% of the best scalar’s implementation energy. The scalar design that consumes the least energy is a four-round implementation. The scalar design that uses the least area and power is the one-round implementation. Balancing energy and area, the two-round pipelined implementation is optimal for a continuous stream of data. One-round and two-round scalar implementations are recommended for intermittent data applications.
Detecting and classifying a brain tumor is a challenge that consumes a radiologist's time and effort while requiring professional expertise. To resolve this, deep learning techniques can be used to help automate the process. The aim of this paper is to enhance the accuracy of brain tumor classification using a new layered architecture of deep neural networks rather than the current state-of-the-art algorithms. In this paper, we propose automated tumor classification by concatenating two convolutional neural network structures of layers and tuning the hyperparameters by utilizing Bayesian optimization. The proposed solution focuses on enhancing the accuracy of classifying tumors to increase the level of trust in the technologies employed in the medical field. The work is tested and evaluated to predict the classification of magnetic resonance imaging inputs and achieving a higher accuracy (97.37%) than other similar works, with accuracies between 84.19% and 96.13%, for the same dataset.
Background Here propose a computer-aided diagnosis (CAD) system to differentiate COVID-19 (the coronavirus disease of 2019) patients from normal cases, as well as to perform infection region segmentation along with infection severity estimation using computed tomography (CT) images. The developed system facilitates timely administration of appropriate treatment by identifying the disease stage without reliance on medical professionals. So far, this developed model gives the most accurate, fully automatic COVID-19 real-time CAD framework. Results The CT image dataset of COVID-19 and non-COVID-19 individuals were subjected to conventional ML stages to perform binary classification. In the feature extraction stage, SIFT, SURF, ORB image descriptors and bag of features technique were implemented for the appropriate differentiation of chest CT regions affected with COVID-19 from normal cases. This is the first work introducing this concept for COVID-19 diagnosis application. The preferred diverse database and selected features that are invariant to scale, rotation, distortion, noise etc. make this framework real-time applicable. Also, this fully automatic approach which is faster compared to existing models helps to incorporate it into CAD systems. The severity score was measured based on the infected regions along the lung field. Infected regions were segmented through a three-class semantic segmentation of the lung CT image. Using severity score, the disease stages were classified as mild if the lesion area covers less than 25% of the lung area; moderate if 25–50% and severe if greater than 50%. Our proposed model resulted in classification accuracy of 99.7% with a PNN classifier, along with area under the curve (AUC) of 0.9988, 99.6% sensitivity, 99.9% specificity and a misclassification rate of 0.0027. The developed infected region segmentation model gave 99.47% global accuracy, 94.04% mean accuracy, 0.8968 mean IoU (intersection over union), 0.9899 weighted IoU, and a mean Boundary F1 (BF) contour matching score of 0.9453, using Deepabv3+ with its weights initialized using ResNet-50. Conclusions The developed CAD system model is able to perform fully automatic and accurate diagnosis of COVID-19 along with infected region extraction and disease stage identification. The ORB image descriptor with bag of features technique and PNN classifier achieved the superior classification performance.
Multipliers are considered critical functional units in many systems like DigitalSignal Processing (DSP), machine learning, and so on. The overall performance of such systems are dependent on the efficiency of multipliers. However, multipliers are slow and power inefficient components due to their complex circuits, so we aim to reduce their power consumption by relaxing their accuracy requirements and at the same time enhancing their speed. In this paper, we present a fast and a power-aware multiplier that targets error-resilient systems. This is achieved by using our proposed approximation algorithm, a hybrid Wallace tree technique for reducing power consumption, and a hybrid ripple-carry adder for reducing latency. The proposed approximation algorithm is implemented using both a modified bit-width aware and carry-in prediction technique, while the proposed hybrid Wallace tree is implemented using high order counters. These proposed algorithms are implemented using HDL language, synthesized, and simulated using Quartus and Modelsim tools. For a 16-bit multiplier, a mean accuracy of 98.35% to 99.95% was achieved with a 45.77% reduction in power, a 21.48% drop in latency, and a 34.95% reduction in area. In addition, our design performs even better for larger size multipliers (32bit multiplier) where a 61.24% reduction in power was achieved, with an 8.74%drop in latency and a 35.24% reduction in area with almost no loss in accuracy. /journal/cta to overcome common performance metrics such as area, speed, and/or power consumption. Booth algorithm, 1 Wallace tree, 2,3 Dadda tree, 4 and array multiplier 5 are examples of such designs. Wallace tree multiplier is one of the best parallel designs used to reduce the multiplier's latency by adding partial products in parallel.Applications including multimedia, 6 neural networks, 7 DSP filtering, 8 and machine learning are error tolerant and do not require a perfect accuracy in computation; hence, getting an approximate result is sufficient. In multimedia applications, as an example, getting precise results is not always required because human observation is limited. For such applications, implementations can be relaxed in order to reduce power consumption, accelerate computations, and minimize area, thus, achieving better performance. Approximate computing is an emerging computing paradigm to enhance the performance of error-tolerant applications. 9-11 According to Han and Orshansky, 10 applications suitable for approximate computing can be classified into four classes: applications with analog inputs, applications with analog outputs, applications with no unique answers, and lastly iterative and convergent applications.Adders and multipliers are the two main components used for approximations. Many research works have been conducted on approximate implementations that are based on adders and can be found in Gupta et al, Zhu et al, On the other hand, fewer works exist in the field of approximate multipliers. Some algorithms used for approximate multipliers are truncation, ...
Steganography has become an important method for concealed communication especially through image files. Recent proposed steganographic methods employ multiple levels of complex techniques. Hence, there is an increasing significance for hardware implementation and its performance metrics. The objective of this article is to analyze and model the performance of FPGA hardware implementations of several spatial steganography methods, including: least significant bit (LSB), random LSB, mix-bit LSB and texture method. This paper presents innovative models to estimate energy-to-embed-secret-bit, peak signal-to-noise-ratio (PSNR) energy cost, power and resources in complex systems. Examining the performance results of the FPGA implementations shows that embedding misalignment degrades the performance, and random embedding increases resources by 43% and power by 13%. Furthermore, the mix-bit method has the best results in terms of balancing the energy consumption and PSNR. Moreover, the accuracy of the model to predict the energy to embed a single secret bit is 2%, and the accuracy of the model to predict complex system performance is 1% for hardware resources and 16.6% for power.
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