Analysis and Modeling of Fpga Implementations of Spatial Steganography Methods

Abstract

Steganography has become an important method for concealed communication especially through image files. Recent proposed steganographic methods employ multiple levels of complex techniques. Hence, there is an increasing significance for hardware implementation and its performance metrics. The objective of this article is to analyze and model the performance of FPGA hardware implementations of several spatial steganography methods, including: least significant bit (LSB), random LSB, mix-bit LSB and texture method. This paper presents innovative models to estimate energy-to-embed-secret-bit, peak signal-to-noise-ratio (PSNR) energy cost, power and resources in complex systems. Examining the performance results of the FPGA implementations shows that embedding misalignment degrades the performance, and random embedding increases resources by 43% and power by 13%. Furthermore, the mix-bit method has the best results in terms of balancing the energy consumption and PSNR. Moreover, the accuracy of the model to predict the energy to embed a single secret bit is 2%, and the accuracy of the model to predict complex system performance is 1% for hardware resources and 16.6% for power.

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“…Implementations were designed and analyzed based on advanced design flow similar to design flows used in other research works such as [36][37][38][39][40]. The design flow is summarized as follows:…”

“…VCD files are fed to Quartus-II tool to compute design power. This technique is commonly used in research works such as [36][37][38][39][40] and [34]. The reported power is mainly the core dynamic power which includes combinational logic power, clock tree power and register power.…”

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“…Step- (8), it is possible to reduce the total time required for embedding all the bits of Message Cache as shown in Figure 4.…”

“…However, the performance would have been better with parallelism in terms of area and time. Mohd et al [8] demonstrate the FPGA hardware implementation in spatial domain Steganography. Simulation, synthesis, and analysis show that random embedding increases utilization of LEs.…”

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“…The FPGA design adheres to a predefined design flow to illustrate and justify the design results. Published FPGA studies typically highlight their design flow [ 60 , 61 ]. Figure 4 illustrates the research design flow, which consists of the design and analysis phases.…”