Abstract-Reliability analysis has become a tool of fundamental importance to virtually all electrical and computer engineers because of the extensive usage of hardware systems in safety and mission critical domains, such as medicine, military, and transportation. Due to the strong relationship between reliability theory and probabilistic notions, computer simulation techniques have been traditionally used to perform reliability analysis. However, simulation provides less accurate results and cannot handle large-scale systems due to its enormous CPU time requirements. To ensure accurate and complete reliability analysis and thus more reliable hardware designs, we propose to conduct a formal reliability analysis of systems within the sound core of a higher order logic theorem prover (HOL). In this paper, we present the higher order logic formalization of some fundamental reliability theory concepts, which can be built upon to precisely analyze the reliability of various engineering systems. The proposed approach and formalization is then utilized to analyze the repairability conditions for a reconfigurable memory array in the presence of stuck-at and coupling faults.

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Mixed-Signal extensions to VHDL, Verilog, and SystemC languages have been developed in order to provide a unifying environment for the modeling and verification of Analog and Mixed Signal (AMS) designs at different levels of abstraction. In this paper, we model the behavior of a set of benchmark designs in VHDL-AMS, Verilog-AMS and SystemC-AMS and compare the simulation performance with HSPICE. The various experimental results observed for the benchmark circuits show the superiority of VHDL-AMS and Verilog-AMS against SystemC-AMS and HSPICE in terms of simulation runtimes at lower level of abstraction.

Abstract. Expectation (average) properties of continuous random variables are widely used to judge performance characteristics in engineering and physical sciences. This paper presents an infrastructure that can be used to formally reason about expectation properties of most of the continuous random variables in a theorem prover. Starting from the relatively complex higher-order-logic definition of expectation, based on Lebesgue integration, we formally verify key expectation properties that allow us to reason about expectation of a continuous random variable in terms of simple arithmetic operations. In order to illustrate the practical effectiveness and utilization of our approach, we also present the formal verification of expectation properties of the commonly used continuous random variables: Uniform, Triangular and Exponential.

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Analog and mixed signal (AMS) circuits play an important role in today's System on Chip design. They pose, however, many challenges in the verification of the overall system due to their complex behavior. Among many developed verification techniques, runtime verification has been shown to be effective by experimenting finite executions instead of going through the whole state space. In this paper, we present a methodology for the specification and verification of AMS designs using online monitoring at runtime based on the notion of System of Recurrence Equations (SREs). We implement the proposed methodology in a C language based tool, called C-SRE, and utilize it to verify several properties of a PLL design. We compare our proposed online monitoring techniques with the offline approach. Finally, we apply the proposed methodology to monitor the jitter noise associated with a voltage controlled oscillator.

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