Constant time arbitrary length synchronous binary counters

Exploration of 2D Cellular Automata as Binary Sequence Generators

“…The counter was developed using Xilinx development boards. Although FPGA devices are not ideal for the evaluation of the CA based sequence generators' performance, it is expected that even this technology can prove the CA sequence generators superiority in terms of performance compared to alternative implementations [5]- [6].…”

Designs of counters with near minimal counting/sampling period and hardware complexity

“…If the number of bits required is smaller than 12, we simply remove flip-flops, and the associated HAs and AND gates, that are not needed. Each of the sections includes an incrementer, which is implemented as a carry-ripple adder with addend 1, the same as a carry-ripple counter with input 1 or a carry-anticipate counter [ 18]. The enable signal of each section is the logical AND of carry-out signals from all the previous sections.…”

“…Binary counters proposed by Vuillemin [18] have counting period equal to the delay of two 3-input gates plus the loading time of a flip-flop, and have cost equal to log 2 m flip-flops and half adders plus a small number of AND gates. They use about half as many flip-flops as the constant-time designs given in [4], but their maximum counting/sampling rates are only half those of the designs in [4], which have counting/sampling periods equal to the delay of an HA plus the loading time of a flip-flop.…”

“…In this paper, we first propose carry-select counters, whose counting/sampling rates are approximately double those of the designs proposed in [18], while achieving similarly low cost. We then propose a novel technique called postponed readout to further increase the counting and sampiing rates.…”

“…In this section we present carry-select counters, a variant of the binary counters proposed in [ 18], while increasing the maximum counting and sampling rate by a factor of about 2.…”