Long and fast up/down counters

Abstract

This paper presents recent advances in the design of constant-time up/down counters in the general context of fast counter design. An overview of existing techniques for the design of long and fast counters reveals several methods closely related to the design of fast adders, as well as some techniques that are only valid for counter design. The main idea behind the novel up/down counters is to recognize that the only extra difficulty with an up/down (vs. up-only or down-only) counter is when the counter changes direction from counting up to counting down (and vice-versa). For dealing with this difficulty, the new design uses a "shadow" register for storing the previous counter state. When counting only up or only down, the counter functions like a standard up-only or down-only constant time counter, but, when it changes direction instead of trying to compute the new value (which typically requires carry propagation), it simply uses the contents of the shadow register which contains the exact desired previous value. An alternative approach for restoring the previous state in constant time is to store the carry bits in a Carry/Borrow register.

Exploration of 2D Cellular Automata as Binary Sequence Generators

“…The counter was developed using Xilinx development boards. Although FPGA devices are not ideal for the evaluation of the CA based sequence generators' performance, it is expected that even this technology can prove the CA sequence generators superiority in terms of performance compared to alternative implementations [5]- [6].…”

Implementation of high speed energy efficient 4-bit binary CLA based incrementer decrementer

“…Various energy efficient high speed adder topologies have been proposed to implement addition operation. Adder forms an essential component of many VLSI systems such as digital signal processors (DSP), microprocessors, ALUs, floating point arithmetic units, memory addressing units, program counters [1], frequency dividers [2] and MAC units. Such high performance devices need low power and area efficient adder circuits.…”

Selective Clock-Gating for Low Power/Low Noise Synchronous Counters

“…Then, the noise and power introduced by the extra hardware is much less than the noise and power we can save. Some efforts have been made to speed long counters using partitioning [9]. Our interest here is not this but to study how noise and power can be reduced when we partition the counter in several parts.…”