Designs of counters with near minimal counting/sampling period and hardware complexity

Yeh, Chi‐Hsiang; Parhami, Behrooz; Wang, Y.

doi:10.1109/acssc.2000.910642

Cited by 5 publications

(2 citation statements)

References 16 publications

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“…The article [9] proposes binary composite counters with the selective carry (Carry-Select Counters), whose performance speed is quite close in value to the counters with parallel operation. However, the amount of the necessary hardware expenses proved to be too large.…”

Section: Literature Review and Problem Statementmentioning

confidence: 99%

“…There were also practically no schemes, which protected the counter from the noises, which, with an increase in speed, tend to grow. Additional shortcoming of the counters, given in the paper [9], is impossibility to read the data immediately after the end of calculation, which complicates compatibility of such computing devices with other digital devices.…”

Section: Literature Review and Problem Statementmentioning

confidence: 99%

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Optimal synthesis of digital counters in the fibonacci codes with the minimal form of representation

Borysenko

Kulyk

Matsenko

et al. 2016

EEJET

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4contrast to the noise-immune systems, binary, decimal and other, similar to them, usual number systems do not possess information redundancy. But they have simple structure, which simplifies their fulfillment of arithmetical and logical operations. Especially distinguished by its simplicity is the binary number system, which, due to it, is so wide-spread today in the practice for developing digital devices and systems.In some cases, the number systems with information redundancy, in addition to providing noise immunity to the digital devices that use it, increase their performance speed while solving a number of special problems. As a result, there appears a possibility for the digital systems, which use such devices, to achieve, in the same codes, a start-to-finish control of information processing and transmission. Their efficiency thus considerably increases both from the point of view of the control of errors in the data processed by them, and the speed of their processing. In this case, a required amount of hardware expenses can be reduced, which, in its turn, leads to the improved reliability of the systems. A useful feature of digital devices, which function in the noise-immune number systems, is also the fact that the redundancy in them, necessary for detection of errors, is evenly distributed in the structures of their schemes, which gives them homogeneity, and, therefore, technological efficiency of their 4  O.

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Section: Literature Review and Problem Statementmentioning

confidence: 99%

Section: Literature Review and Problem Statementmentioning

confidence: 99%

Optimal synthesis of digital counters in the fibonacci codes with the minimal form of representation

Borysenko

Kulyk

Matsenko

et al. 2016

EEJET

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A 2.4-GHz low-power all-digital phase-locked loop

Xu¹,

Lindfors²,

Stadius³

et al. 2009

2009 IEEE Custom Integrated Circuits Conference

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This paper presents a 2.4-GHz all-digital phaselocked loop (ADPLL) frequency synthesizer for wireless applications. The ADPLL is built around a digitally controlled LC oscillator, and it covers the target frequency range with fine frequency resolution. In the feedback path, a high-speed topology is employed for the variable phase accumulator to count full cycles of the RF output. A simple technique based on a short delay line in the reference signal path effectively lowers power consumption of the time-to-digital converter (TDC) and reduces in-band spurs of the output spectrum. Fabricated in a 65-nm CMOS, the ADPLL has an active area of 0.24 mm 2 . Measured output frequency range is from 2.29 to 2.92 GHz. The worstcase phase noise at 1-MHz offset over the whole frequency range is -120 dBc/Hz when the PLL consumes 12 mW from a 1.2-V supply, and -112 dBc when power is lowered to 8 mW. The inband spurs are below -61 dBc, and far-off spurs below -57 dBc.

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