A 2.4-GHz low-power all-digital phase-locked loop

Abstract

This paper presents a 2.4-GHz all-digital phaselocked loop (ADPLL) frequency synthesizer for wireless applications. The ADPLL is built around a digitally controlled LC oscillator, and it covers the target frequency range with fine frequency resolution. In the feedback path, a high-speed topology is employed for the variable phase accumulator to count full cycles of the RF output. A simple technique based on a short delay line in the reference signal path effectively lowers power consumption of the time-to-digital converter (TDC) and reduces in-band spurs of the output spectrum. Fabricated in a 65-nm CMOS, the ADPLL has an active area of 0.24 mm 2 . Measured output frequency range is from 2.29 to 2.92 GHz. The worstcase phase noise at 1-MHz offset over the whole frequency range is -120 dBc/Hz when the PLL consumes 12 mW from a 1.2-V supply, and -112 dBc when power is lowered to 8 mW. The inband spurs are below -61 dBc, and far-off spurs below -57 dBc.

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

“…ADPLL implementations also include Refs. [6], [7], [8], [10], [11], [12], [13], [14] and [25]. It should be noted that there have been reported other all-digital PLL implementations, such as Refs.…”

“…1 (a); and feedback-divider-less counter-based topology [3], [4], [5], [10], [11], [12], [13], [14], [15], [16], as shown in Fig. 1 (b).…”

“…In Refs. [19] and [13], the K T DC estimation is a result of a non-iterative calculation that involves a fixed-point divider, which makes it more complex. In fact, this apparent complexity has led to develop a new class of a highercomplexity TDC that does not require normalization [40].…”

An all-digital PLL with supply insensitive digitally controlled oscillator

“…1 shows a typical divider-less ADPLL. It has a linear phase detector (LPD), which can calculate the phase difference between the reference and oscillator clocks in a unit of the oscillator clock period, independent of the amounts of the phase error [2,3,4]. We propose a simple phase detector (PD) operating in the manner of interleaving of two asynchronous down counters, which consumes smaller area and dissipates less power compared to synchronous accumulators.…”

“…It also takes a long time to design a new circuit or to revise the existing version for the next generation process with the analog components. Various all-digital PLLs, which make the best use of digital signal processing around the loop, have been developed recently [2,3,4,5] to overcome aforementioned problems. Digital circuits, however, deteriorate the phase noise performance because of its finite resolution.…”