An all-digital PLL with supply insensitive digitally controlled oscillator

Abstract

This paper presents a divider-less all-digital PLL (ADPLL) with supply insensitivity. We employ a feed-forward inverter to make the oscillator insensitive to supply variation and utilize the delta-sigma modulation to improve the resolution. The onchip calibration tracks the optimum compensation strength for process and nominal voltage variations. We use an asynchronous counter to decide the phase error for low power. The proposed ADPLL was fabricated in a 0.13 m CMOS process. The silicon area of the ADPLL is 0.26 mm 2 and the power consumption is 5.8 mW at 320 MHz. The spur level with the proposed compensation scheme was improved from À57 dBc to À84 dBc with an intentional supply noise.