An accumulative parallel counter represents (I true generalization of a sequential counter in that it incorporates the memory feature of an ordinary counter: i.e., it a&& the sum of its n binary inputs to a stored value. We examine the design of accumulative parallel counters and show that direct synthesis of such a counter, as opposed to bdding it from a combinational parallel counter and a fast adder, leads to significant reduction in complexity and delay.
While the mere fact that savings can be achieved coines as no surprise to seasoned arithmetic &signers, its extent and consequences in designing large-scale (systolic) associative processors, modular multi-operand adders, serial-pwallel multipliers, and digital neural networks merits dttailed examination. Both simple accumulative parallel counters and their modular versions, that keep the accumulated count modulo an arbitrary constant p , are dealt with.
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