Congestion estimation during top-down placement

Yang, Xiaojian; Kastner, Ryan; Sarrafzadeh, Majid

doi:10.1145/369691.369761

Cited by 54 publications

(59 citation statements)

References 16 publications

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“…In [15], the authors propose a stochastic congestion estimation algorithm for a placed netlist. In [24], Rent's rule is used to quantitatively estimate the maximum congestion prior to the placement stage. None of these methods can be applied to optimize for congestion since it is difficult to capture Rent's exponent during structural transformations.…”

Section: Capturing Routing Congestion From Netlist Structure 31 Prevmentioning

confidence: 99%

Pre-layout wire length and congestion estimation

Liu

Marek-Sadowska

2004

Proceedings of the 41st Annual Design Automation Conference

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In this paper, we study the pre-layout wire length and congestion estimation. We find that two structural metrics, mutual contraction and net range, can be used to predict wire lengths. These metrics have different application ranges and complement each other. We also propose a new metric, the structural pin density, to capture the peak routing congestion of designs. Larger maximum pin densities usually lead to larger peak congestions in circuits with similar average congestions. We demonstrate experimentally very good correlation of our pre-layout measures with post layout interconnect lengths. We also isolate the structural netlist properties which cause the peak congestion.

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Section: Capturing Routing Congestion From Netlist Structure 31 Prevmentioning

confidence: 99%

Pre-layout wire length and congestion estimation

Liu

Marek-Sadowska

2004

Proceedings of the 41st Annual Design Automation Conference

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“…Previous works on routing congestion estimation at the early stages of physical design have been proposed [2][3][4]. Most of them [2,4] were implemented at placement stage; authors of [3] proposed a estimation method at floorplan stage.…”

Section: Introductionmentioning

confidence: 99%

“…Most of them [2,4] were implemented at placement stage; authors of [3] proposed a estimation method at floorplan stage. However, the computation of estimation at floorplan stage takes several to dozens of seconds while at placement stage it usually uses more than hundreds of seconds.…”

Section: Introductionmentioning

confidence: 99%

Effective Estimation Method of Routing Congestion at Floorplan Stage for 3D ICs

Ahn¹,

Kim²,

Li³

et al. 2011

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Higher integrated density in 3D ICs also brings the difficulties of routing, which can cause the routing failure or re-design from beginning. Hence, precise congestion estimation at the early physical design stage such as floorplan is beneficial to reduce the total design time cost. In this paper, an effective estimation method of routing congestion is proposed for 3D ICs at floorplan stage. This method uses synthesized virtual signal nets, power/ground network and clock network to achieve the estimation. During the synthesis, the TSV location is also under consideration. The experiments indicate that our proposed method had small difference with the estimation result got at the post-placement stage. Furthermore, the comparison of congestion maps obtained with our method and global router demonstrates that our estimation method is able to predict the congestion hot spots accurately.

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“…This category includes bounding-box (BBOX)-based modeling [12], probabilistic analysis-based modeling [17,14], Rent's rule-based modeling [24], and pin density-based modeling [5]. TP-based modeling methods usually construct Steiner tree for each net in the netlist.…”

Section: Congestion Estimationmentioning

confidence: 99%

Routability-driven placement and white space allocation

Xie

Koh

et al.

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.

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In this paper, we present a congestion-driven placement flow. First, we consider in the global placement stage the routing demand to replace cells in order to avoid congested regions. Then we allocate appropriate amounts of white space into different regions of the chip according to the congestion map. Finally, a detailed placer is applied to legalize placements while preserving the distributions of white space. Experimental results show that our placement flow can achieve the best routabilities with shorter routed wirelengths among publicly available placement tools. Moreover, our white space allocation approach can significantly improve the routability of placements generated by other placement tools.

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Congestion estimation during top-down placement

Cited by 54 publications

References 16 publications

Pre-layout wire length and congestion estimation

Pre-layout wire length and congestion estimation

Effective Estimation Method of Routing Congestion at Floorplan Stage for 3D ICs

Routability-driven placement and white space allocation

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