Pre-layout wire length and congestion estimation

Liu, Qinghua; Marek-Sadowska, Malgorzata

doi:10.1145/996566.996726

Cited by 24 publications

(18 citation statements)

References 25 publications

(24 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As shown in Column 7, the number of cells in the congestionaware mapped netlists have decreased slightly in all cases but that of C432. The decrease in the number of cells can be associated with the corresponding reduction in the number of nets, which may be indirectly correlated with metrics such as structural pin-density, and hence, congestion, as pointed out in [14]. In case of C432, however, employing more logic cells has resulted in the congestion alleviation, which can be explained using the discussion in the previous remark on the average row utilization.…”

Section: Analysis Of Experimental Resultsmentioning

confidence: 77%

“…Other related work lies in the domain of structural logic synthesis [13,14], where metrics for routing congestion are proposed to guide the logic synthesis. An adhesion is presented as a metric for routing congestion in [13], while structural pin density is shown to correlate well with congestion in [14]. The adhesion, being computationally expensive, may not be suitable for technology mapping purposes.…”

Section: Previous Workmentioning

confidence: 99%

“…Just as the gate-area for entire network cannot be predicted until the end of the matching phase in [5], so is the inability of the dynamic programming framework in our work to predict the congestion map of entire network until the end of the matching. Of course, compared to a metric like gate-area, the routing congestion optimization objective is far more complicated, as noted in several recent works [9,11,13,14]. We also employ a better delay computation approach as compared to [5].…”

Section: Analogy With the Classical Matchingmentioning

confidence: 99%

See 2 more Smart Citations

An efficient technology mapping algorithm targeting routing congestion under delay constraints

Shelar

Saxena

Wang

et al. 2005

Proceedings of the 2005 International Symposium on Physical Design

View full text Add to dashboard Cite

Routing congestion has become a serious concern in today's VLSI designs. In this paper, we propose a technology mapping algorithm that minimizes routing congestion under delay constraints. The algorithm employs a dynamic programming framework in the matching phase to generate probabilistic congestion maps for all the matches. These congestion maps are then utilized to minimize routing congestion during the covering, which preserves the delayoptimality of the solution using the notion of slack. Experimental results on benchmark circuits in a 100 nm technology show that the algorithm can improve track overflows by 44%, on an average, as compared to the conventional technology mapping while satisfying delay constraints.

show abstract

Section: Analysis Of Experimental Resultsmentioning

confidence: 77%

Section: Previous Workmentioning

confidence: 99%

Section: Analogy With the Classical Matchingmentioning

confidence: 99%

See 1 more Smart Citation

An efficient technology mapping algorithm targeting routing congestion under delay constraints

Shelar

Saxena

Wang

et al. 2005

Proceedings of the 2005 International Symposium on Physical Design

View full text Add to dashboard Cite

show abstract

“…Probabilistic congestion estimation techniques have been shown to successfully guide design optimization choices at various stages of physical design, including placement [10][11][12] and logic-synthesis [14,15]. Our novel approach extends and improves upon Steiner heuristic called the single trunk Steiner tree (STST) [16], leveraging it for wiring and congestion estimation at the standard-cell level.…”

Section: A Backgroundmentioning

confidence: 99%

A methodology for the early exploration of design rules for multiple-patterning technologies

Ghaida

Sahu

Kulkarni

et al. 2012

Proceedings of the International Conference on Computer-Aided Design

View full text Add to dashboard Cite

Abstract-Double/Multiple-patterning (DP/MP) lithography in a multiple litho-etch steps process is a favorable solution for technology scaling to the 20nm node and below. Mask-assignment conflicts represent the biggest challenge for MP and limiting them through design rules is crucial for the adoption of MP technology. In this paper, we offer a methodology for the early evaluation and exploration of layout and MP rules intended for speeding up the rules-development cycle. Using a novel wiringestimation method, we create layout estimates with fine-grained congestion prediction. MP-conflicts are then predicted using a machine-learning approach. In this work, we demonstrate the use of the method for double-patterning lithography in litho-etchlitho-etch process; the methodology is more general, however, and can be applied for other multiple-patterning technologies including tripe/multiple-patterning with multiple litho-etch steps, selfaligned double patterning (SADP), and directed self-assembly. Results of testing the methodology on standard-cell layouts show an 81% accuracy in DP-conflicts prediction. The methodology was then used to explore DP and layout rules and investigate their effects on DP-compatibility and layout area. The methodology allows for rules optimization; for example, pushing the minimum tip-to-side same-color spacing rule value from 1.7× to 1.5× the minimum side-to-side spacing design rule (i.e., from 110nm down to 90nm) would more than double the number of DP-compatible cells in the library.

show abstract

“…The net-by-net length predictions can be used to optimize designs through clustering and placement stages, or to construct performance models before and after the clustering stage for design space exploration. The set of structural metrics considered have been validated over ASIC placers and benchmark suites [7], [8], [9]. These are applicable to FPGAs as their definitions do not capture domain specific information.…”

Section: Ali Akoglumentioning

confidence: 99%

Wirelength Prediction for FPGAs

Pandit

Akoglu

2007

2007 International Conference on Field Programmable Logic and Applications

View full text Add to dashboard Cite

FPGA CAD tools require wirelength predictions to make informed decisions through clustering, placement and routing stages towards power, area or delay based design goals. Unfortunately, there has been minimal work devoted to estimating individual wirelengths early in the CAD flow. Rent's rule can be used to generate a wirelength distribution but cannot be used to predict lengths of individual wires. Hence, this paper explores "structural metrics" that have been found to possess strong predictive qualities in the ASIC domain. To our knowledge this is a first study in the application of these metrics in the FPGA CAD flow. Results show that the studied metrics capture characteristics of placement optimization carried out by VPR, and hence, are good indicators of post-placement wirelengths.

show abstract

Pre-layout wire length and congestion estimation

Cited by 24 publications

References 25 publications

An efficient technology mapping algorithm targeting routing congestion under delay constraints

An efficient technology mapping algorithm targeting routing congestion under delay constraints

A methodology for the early exploration of design rules for multiple-patterning technologies

Wirelength Prediction for FPGAs

Contact Info

Product

Resources

About