Wirelength Prediction for FPGAs

Pandit, A.; Akoglu, Ali

doi:10.1109/fpl.2007.4380760

Cited by 8 publications

(9 citation statements)

References 17 publications

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“…If no related block is available and only if the current utilization level is less than the "unrelated block threshold" (UBT), T-NDPack allows clustering the unrelated block (Ln. [13][14]. This rule avoids clustering very few unrelated blocks and the possible inter-CLB delay.…”

Section: Unrelated Block Clusteringmentioning

confidence: 97%

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T-NDPack: Timing-driven non-uniform depopulation based clustering

Liu

Akoglu

2009

2009 5th Southern Conference on Programmable Logic (SPL)

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Low-cost FPGAs have comparable number of Configurable Logic Blocks (CLBs) with respect to resource-rich FPGAs but have much less routing tracks. This leads to the difficulty for CAD tools to successfully and optimally map a circuit into these devices. Instead of switching to resource-rich FPGAs, the designers could employ depopulation based clustering technique which underuses CLBs, hence improves routability by spreading the logic over the architecture. However, all depopulation based clustering algorithms to this date increase critical path delay. In this paper, we present a timing-driven non-uniform depopulation based clustering technique, T-NDPack, that targets critical path delay and channel width constraints simultaneously. We adjust the capacity of the CLB based on the criticality of the logic block. Paper analyzes the effect of depopulation strategies on area and delay performance. Results show that T-NDPack reduces minimum channel width by 11.07% while increasing the number of CLBs by 13.28%. More importantly, TNDPack decreases critical path delay by 2.89%.

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Section: Unrelated Block Clusteringmentioning

confidence: 97%

“…If the related block is not available and clustering the unrelated blocks is allowed, T-NDPack clusters the unrelated block with the highest gain value (Ln. [13][14]. (e) Finally, T-NDPack removes the block from the unclustered block list with the next iteration.…”

Section: Algorithm Flowmentioning

confidence: 99%

T-NDPack: Timing-driven non-uniform depopulation based clustering

Liu

Akoglu

2009

2009 5th Southern Conference on Programmable Logic (SPL)

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“…In [17,18], Pandit introduces a wirelength prediction techni-que that accurately estimates postplacement individual wirelength information for a given netlist before the clustering stage. As future work, we plan to incorporate this mechanism into our clustering cost function to further improve the performance of the T-NDPack.…”

Section: Discussionmentioning

confidence: 99%

Timing-Driven Nonuniform Depopulation-Based Clustering

Liu

Akoglu

2010

International Journal of Reconfigurable Computing

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Low-cost FPGAs have comparable number of Configurable Logic Blocks (CLBs) with respect to resource-rich FPGAs but have much less routing tracks. For CAD tools, this situation increases the difficulty of successfully mapping a circuit into the lowcost FPGAs. Instead of switching to resource-rich FPGAs, the designers could employ depopulation-based clustering techniques which underuse CLBs, hence improve routability by spreading the logic over the architecture. However, all depopulation-based clustering algorithms to this date increase critical path delay. In this paper, we present a timing-driven nonuniform depopulationbased clustering technique, T-NDPack, that targets critical path delay and channel width constraints simultaneously. T-NDPack adjusts the CLB capacity based on the criticality of the Basic Logic Element (BLE). Results show that T-NDPack reduces minimum channel width by 11.07% while increasing the number of CLBs by 13.28% compared to T-VPack. More importantly, T-NDPack decreases critical path delay by 2.89%.

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“…At the high-level synthesis stage, power estimation has been done to drive low-power resource allocation and binding techniques [6]. At the preplacement stage, work has been done to predict interconnect wirelength and delay [8,13]. The work by Manohararajah et al [8] proposed a simple timing model based on using a single delay value for each connection depending on its source and destination node type and port (e.g.…”

Section: Early Delay/power Predictionmentioning

confidence: 99%

“…logic, I/O, memory). The work by Pandit and Akoglu [13] attempts to estimate wirelengths using structural metrics at the preplacement stage -metrics taken from works in the ASIC domain and applied to FPGAs.…”

Section: Early Delay/power Predictionmentioning

confidence: 99%

Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and power

Shum

Anderson

2012

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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FPGA CAD algorithms are heuristic, and generally make use of cost functions to gauge the value of one potential circuit implementation over another. At times, such algorithms must decide between two or more implementation options of apparently equal cost. This work explores the variations in circuit quality, i.e. noise, that arise when CAD algorithms are altered to choose randomly when faced with such equal-cost alternatives. Noise sources are identified in logic synthesis and technology mapping algorithms, and experimental results are presented which show standard deviations of 3.3% and 3.7% from the mean in post-routed delay and power. As a means of dealing with this variation, early timing and power prediction metrics can be applied after technology mapping to find the best circuits in the presence of noise. When applied to designs with over 1.5% variation in delay and power, the best prediction models have a 40% probability of capturing the best circuit when predicting the top 10% of circuits in a group of noise-injected circuits.

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Wirelength Prediction for FPGAs

Cited by 8 publications

References 17 publications

T-NDPack: Timing-driven non-uniform depopulation based clustering

T-NDPack: Timing-driven non-uniform depopulation based clustering

Timing-Driven Nonuniform Depopulation-Based Clustering

Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and power

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