Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and power

Abstract

FPGA CAD algorithms are heuristic, and generally make use of cost functions to gauge the value of one potential circuit implementation over another. At times, such algorithms must decide between two or more implementation options of apparently equal cost. This work explores the variations in circuit quality, i.e. noise, that arise when CAD algorithms are altered to choose randomly when faced with such equal-cost alternatives. Noise sources are identified in logic synthesis and technology mapping algorithms, and experimental results are presented which show standard deviations of 3.3% and 3.7% from the mean in post-routed delay and power. As a means of dealing with this variation, early timing and power prediction metrics can be applied after technology mapping to find the best circuits in the presence of noise. When applied to designs with over 1.5% variation in delay and power, the best prediction models have a 40% probability of capturing the best circuit when predicting the top 10% of circuits in a group of noise-injected circuits.

Sources of bias in EDA tools and its influence

“…These heuristics can be influenced by many external aspects and results of different quality can be produced under different circumstances. In this paper we will show an experimental evaluation of several tools, to illustrate that the situation is much more severe than previously reported [2], [3].…”

“…We have performed a much more exhaustive evaluation, and we will show in this section, that the reality is much worse than as reported in [2] and [3].…”

“…Authors of [3] also noticed the fact, that algorithms used in synthesis tools (particularly ABC [5], [6]) can have such multiple decisions and aptly call this phenomenon "CAD algorithm noise". They have modified some basic ABC algorithms to perform equally valued decisions randomly, to achieve possibly different solutions.…”

On Robustness of EDA Tools

“…The problem can be attacked bottom-up, by inspection of the code as in [9], or top-down, by injecting all possible perturbations into input descriptions [7], [8].…”

“…As the tools are required to be deterministic, randomization cannot be used to achieve fairness. When it is done, as in [9], it appears to be an additional source of variance. The authors aptly call it "CAD algorithm noise".…”