Conformal Doping of FINFETs: a Fabrication and Metrology Challenge

Abstract

Whereas the introduction of 3D-dimensional devices such as FINFET's may be a solution for next generation technologies, they do represent significant challenges with respect to the doping strategies and the junction characterization.Aiming at a conformal doping of the source/drain regions in a FINFET in order to induce a conformal under diffusion and homogenous device operation, one can quickly recognize that classical beam implants fail to fulfill these needs, in particular when considering closely spaced fin's. Indeed the effects of different implant angles (top vs bottom) and the concurrent variation in projected range, dose retention and sputtering as well as the effect of the wafer rotation when tilting is used, all lead to a non-conformal doping. Alternative processes such as vapor phase deposition (VPD) or plasma doping are presently being considered, as they hold the promise of conformality. Using VPD or Atomic Layer Doping dopant atoms are deposited on the surface through thermal decomposition of typical chemical vapor deposition precursors and are subsequently in diffused. Good conformality (~ 93 % for sidewall vs. top dose), defect free junctions and high activation levels are the positive points of this process. Plasma immersion doping is an alternative approach which is easier to integrate (similar to ion implantation) and suitable for p-and n-type doping. Whereas it holds the promise of conformality when implanting large macroscopic features, the latter is far less obvious when trying to dope microscopic feature conformally. In fact the formation of conformal junctions in FINFET's with plasma based processes is quite challenging and relies on secondary processes such as resputtering, deposition and in diffusion etc. Their optimization is compromised by concurrent artifacts, sputter erosion being the most important one. In support of these developments the measurement and identification of conformality adequate metrology is required. For this purpose we have extensively used Scanning Spreading Resistance Microscopy (SSRM) as a means to characterize the vertical/lateral junction depths, the concentration levels and the degree of conformality. Characterization of the (3D)-underdiffusion can be achieved by a dedicated SSRM experiment and/or the Tomographic Atomprobe. As a complement to the SSRM technique we also developed a concept based on resistance measurements of fin's which allows to map the sidewall doping across the wafers and provides fast feedback on conformality.

Atom probe analysis of a 3D finFET with high-k metal gate

“…In scaled planar technologies the performance is already very sensitive to process variations affecting the structural and material properties such as dimensions, interface roughness and dopant distribution, necessitating advanced metrology to control them very precisely. The latter is for finfets even more aggravated as their 3D structure calls for sub-nanometre metrology techniques with 3D resolution [2,3].…”

The Challenges of Advanced CMOS Process from 2D to 3D

“…For 3D structure devices like FinFETs, the requirement for S/D extension is not limited for highly dopant activation or less dopant diffusion and profile abruptness, but the conformal distribution within the fins [112][113][114]. The non-conformal doping profile results in degradation of the drive current of the transistor.…”

Improved physical models for advanced silicon device processing

“…One of the main challenges is the efficient dopant incorporation into these vertical structures, as it directly affects the parasitic resistance RSD that defines the dynamic performance of FinFETs (high RSD values may limit the maximum drive current) [158,164]. This resistance is controlled by the geometry of the fin and the carrier concentration (determined by electrically active dopants) in the fin.…”

“…Due to trigonometrical considerations, the dose irradiated in the sidewalls is a factor of tan(α) with respect to the dose in the fin top [164].…”

“…In addition, the loss of conformality leads to differences in turn-on behavior and current flow on the top and sidewalls of the fin [164] and increased gate-induced drain leakage currents (a major source of off-state leakage in FinFETs) [161,169].…”