Computational RAM: implementing processors in memory

Elliott, D.G.; Stumm, Michael; Snelgrove, W.M.; Cojocaru, C.; McKenzie, Raymond J.

doi:10.1109/54.748803

Cited by 180 publications

(67 citation statements)

References 9 publications

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“…Several processor-in-memory architectures have been proposed such as the computational RAM (C·RAM) [4], smart memories [5], and intelligent RAM (IRAM) [6]. These approaches maintain the separation between a lowswing/low-SNR memory array and a high-swing/high-SNR logic.…”

Section: Introductionmentioning

confidence: 99%

An energy-efficient VLSI architecture for pattern recognition via deep embedding of computation in SRAM

Kang

Keel

Shanbhag

et al. 2014

2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

123

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In this paper, we propose the concept of compute memory, where computation is deeply embedded into the memory (SRAM). This deep embedding enables multi-row read access and analog signal processing. Compute memory exploits the relaxed precision and linearity requirements of pattern recognition applications. System-level simulations incorporating various deterministic errors from analog signal chain demonstrates the limited accuracy of analog processing does not significantly degrade the system performance, which means the probability of pattern detection is minimally impacted. The estimated energy saving is 63 % as compared to the conventional system with standard embedded memory and parallel processing architecture, for 256×256 target image.

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Section: Introductionmentioning

confidence: 99%

An energy-efficient VLSI architecture for pattern recognition via deep embedding of computation in SRAM

Kang

Keel

Shanbhag

et al. 2014

2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

123

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“…Since PIM processors are usually not as sophisticated as state-of-the-art microprocessors due to on-chip space constraints, systems using PIMs alone in a multiprocessor may sacrifice performance on uniprocessor computations [Saulsbury96] [Kogge94], while SoC (System-on-aChip) solutions (e.g., the IRAM [Patterson97] and the Mitsubishi M32R/D [Mitsubishi99]) limit the application domain. DIVA's support for a broad range of familiar parallel programming paradigms, including task parallelism for irregular computations, distinguishes it from systems with restricted applicability (such as to SIMD parallelism [Elliot99][Gokhale95] [Patterson97]), as well as systems requiring a novel programming methodology or compiler technology to configure logic [Babb99], or to manage a complex memory, computation and communication hierarchy [Kang99]. DIVA's PIM-to-PIM interconnect improves upon approaches that serialize communication through the host, which decreases bandwidth by introducing added traffic on the processor memory bus [Oskin98] [Gokhale95].…”

Section: Introductionmentioning

confidence: 99%

DIVA (Data Intensive Architecture)

Granacki¹,

Hall²,

Draper³

et al. 2004

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Public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing this collection of information. 12b. DISTRIBUTION CODE ABSTRACT (Maximum 200 Words)The design, development and implementation of a prototype system of a novel computer architecture based on PIM (Processing-In-Memory) technology are presented. The simulator and emulator that were used to develop and evaluate the overall concepts and system are also described. The DIVA system uses PIM-based "smart memories" to improve the effective processor-memory bandwidth. The DIVA "smart memory" significantly improves the performance of dataintensive applications over their performance on conventional processor memory systems that suffer from the traditional performance bottleneck caused by the speed gap between high performance microprocessors and DRAMs (Dynamic Random Access Memory) used in main memory. The chips developed for DIVA represent the first smart-memory devices supporting virtual addressing and capable of executing multiple threads of control. DIVA achieves enhanced performance through multiple mechanisms including both coarse-grain and fine-grain parallelism. The simulation results for a broad class of applications run on the DIVA simulator and reported in the literature show significant speedups over conventional processor architectures. Running some of these applications on the prototype hardware has validated these speedups.

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“…Computation in main memory (e.g. Computational RAM [16]) has been studied, but it failed to see much light due to the fast advancement of I/O interfaces. However, in light of power consumption walls and Big Data, moving computation to high capacity secondary storage is becoming an attractive option.…”

Section: Related Workmentioning

confidence: 99%

Scalable multi-access flash store for big data analytics

Jun

Liu

Fleming

et al. 2014

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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For many "Big Data" applications, the limiting factor in performance is often the transportation of large amount of data from hard disks to where it can be processed, i.e. DRAM. In this paper we examine an architecture for a scalable distributed flash store which aims to overcome this limitation in two ways. First, the architecture provides a highperformance, high-capacity, scalable random-access storage. It achieves high-throughput by sharing large numbers of flash chips across a low-latency, chip-to-chip backplane network managed by the flash controllers. The additional latency for remote data access via this network is negligible as compared to flash access time. Second, it permits some computation near the data via a FPGA-based programmable flash controller. The controller is located in the datapath between the storage and the host, and provides hardware acceleration for applications without any additional latency. We have constructed a small-scale prototype whose network bandwidth scales directly with the number of nodes, and where average latency for user software to access flash store is less than 70µs, including 3.5µs of network overhead.

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Computational RAM: implementing processors in memory

Cited by 180 publications

References 9 publications

An energy-efficient VLSI architecture for pattern recognition via deep embedding of computation in SRAM

An energy-efficient VLSI architecture for pattern recognition via deep embedding of computation in SRAM

DIVA (Data Intensive Architecture)

Scalable multi-access flash store for big data analytics

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