An energy-efficient VLSI architecture for pattern recognition via deep embedding of computation in SRAM

Kang, Mingu; Keel, Min-Sun; Shanbhag, Naresh R.; Eilert, Sean; Curewitz, Ken

doi:10.1109/icassp.2014.6855225

Cited by 131 publications

(67 citation statements)

References 8 publications

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“…The MR-READ step begins with the application of access pulses simultaneously to the rows storing a ij and p j such that the pulse width T R BL C BL , where R BL C BL is the RC time constant of BL/BLB [2]. This results in a BL/BLB voltage (see Fig.…”

Section: A Compute Memory-based Address Decoder (Cm-ad)mentioning

confidence: 99%

“…In the MR-READ operation, the V th variations were modeled as a Gaussian distributed random variable in [2]. In this paper, two binary numbers a and p (we omit indices i and j for simplicity) are MR-READ.…”

Section: A Behavioral Modelmentioning

confidence: 99%

“…Recently, we proposed Compute Memory (CM) [2], [3] an inmemory computing architecture, where both computation and storage are implemented in a low swing/low signal-to-noise ratio (SNR) domain thereby eliminating the processor-memory interface completely, and providing a 5.0 × energy reduction and 4.9 × throughput enhancement for pattern recognition application in a 45 nm CMOS process. CM preserves the storage density, the conventional SRAM's read/write functionality, and is well-suited for inference kernels such as SDM which can compensate for non-deterministic hardware operations.…”

Section: Introductionmentioning

confidence: 99%

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In-Memory Computing Architectures for Sparse Distributed Memory

Kang

Shanbhag

2016

IEEE Trans. Biomed. Circuits Syst.

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This paper presents an energy-efficient and high-throughput architecture for Sparse Distributed Memory (SDM)-a computational model of the human brain [1]. The proposed SDM architecture is based on the recently proposed in-memory computing kernel for machine learning applications called Compute Memory (CM) [2], [3]. CM achieves energy and throughput efficiencies by deeply embedding computation into the memory array. SDM-specific techniques such as hierarchical binary decision (HBD) are employed to reduce the delay and energy further. The CM-based SDM (CM-SDM) is a mixed-signal circuit, and hence circuit-aware behavioral, energy, and delay models in a 65 nm CMOS process are developed in order to predict system performance of SDM architectures in the auto- and hetero-associative modes. The delay and energy models indicate that CM-SDM, in general, can achieve up to 25 × and 12 × delay and energy reduction, respectively, over conventional SDM. When classifying 16 × 16 binary images with high noise levels (input bad pixel ratios: 15%-25%) into nine classes, all SDM architectures are able to generate output bad pixel ratios (Bo) ≤ 2%. The CM-SDM exhibits negligible loss in accuracy, i.e., its Bo degradation is within 0.4% as compared to that of the conventional SDM.

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Section: A Compute Memory-based Address Decoder (Cm-ad)mentioning

confidence: 99%

Section: A Behavioral Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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In-Memory Computing Architectures for Sparse Distributed Memory

Kang

Shanbhag

2016

IEEE Trans. Biomed. Circuits Syst.

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“…In the MR-READ operation [1]: (a) d is stored in one column, (b) B D word lines (WLs) are activated per precharge, and (c) the WL access pulse width T k ∝ 2 k (k ∈ [0, B D − 1]), i.e., the access pulses are pulse-width modulated. By ensuring that T k RC, where RC is the time constant of the bit lines BL and BLB, the BLB voltage drop at the end of the MR-READ process is given by [1]:…”

Section: Compute Memory (Cm)mentioning

confidence: 99%

“…Compute memory[1]: (a) architecture, (b) column structure of bit cell array (c) and the MR-READ waveform for 4-bit word read-out, D = 1111b'[1].…”

mentioning

confidence: 99%

An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks

Kang

Gonugondla

Keel

et al. 2015

2015 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

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In this paper, an energy efficient, memory-intensive, and high throughput VLSI architecture is proposed for convolutional networks (C-Net) by employing compute memory (CM) [1], where computation is deeply embedded into the memory (SRAM). Behavioral models incorporating CM's circuit non-idealities and energy models in 45 nm SOI CMOS are presented. System-level simulations using these models demonstrate that the probability of handwritten digit recognition P r > 0.99 can be achieved using the MNIST database [2], along with a 24.5× reduced energy delay product, a 5.0× reduced energy, and a 4.9× higher throughput as compared to the conventional system.

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High‐throughput in‐memory bitwise computing based on a coupled dual‐SRAM array with independent operands

Wu,

Lin,

et al. 2024

Circuit Theory & Apps

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The successful implementation of artificial intelligence algorithms depends on the capacity to execute numerous repeated operations, which, in turn, requires systems with high data throughput. Although emerging computing‐in‐memory (CIM) eliminates the need for frequent data transfer between the memory and processing blocks and enables parallel activation of multiple rows, the traditional structure, where each row has only one identical input value, significantly limits its further application. To solve this problem, this study proposes a dual‐SRAM CIM architecture in which two SRAM arrays are coupled such that all operands are different, thus rendering the use of CIM considerably more flexible. The proposed dual‐SRAM array was implemented through a 55‐nm process, essentially delivering a frequency of 361 MHz for a 1.2‐V supply and energy efficiency of 161 TOPS/W at 0.9 V supply.

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An energy-efficient VLSI architecture for pattern recognition via deep embedding of computation in SRAM

Cited by 131 publications

References 8 publications

In-Memory Computing Architectures for Sparse Distributed Memory

In-Memory Computing Architectures for Sparse Distributed Memory

An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks

High‐throughput in‐memory bitwise computing based on a coupled dual‐SRAM array with independent operands

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