DIVA (Data Intensive Architecture)

Abstract

Public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing this collection of information. 12b. DISTRIBUTION CODE ABSTRACT (Maximum 200 Words)The design, development and implementation of a prototype system of a novel computer architecture based on PIM (Processing-In-Memory) technology are presented. The simulator and emulator that were used to develop and evaluate the overall concepts and system are also described. The DIVA system uses PIM-based "smart memories" to improve the effective processor-memory bandwidth. The DIVA "smart memory" significantly improves the performance of dataintensive applications over their performance on conventional processor memory systems that suffer from the traditional performance bottleneck caused by the speed gap between high performance microprocessors and DRAMs (Dynamic Random Access Memory) used in main memory. The chips developed for DIVA represent the first smart-memory devices supporting virtual addressing and capable of executing multiple threads of control. DIVA achieves enhanced performance through multiple mechanisms including both coarse-grain and fine-grain parallelism. The simulation results for a broad class of applications run on the DIVA simulator and reported in the literature show significant speedups over conventional processor architectures. Running some of these applications on the prototype hardware has validated these speedups.

To PIM or not for emerging general purpose processing in DDR memory systems

“…Earlier specialized PIM solutions such as FlexRAM [38], and DIVA [21] provided compilers [24] [26]. However, most of the work today concentrates on HMC/HBM based implementations where the focus is on mitigating data movement bottlenecks [37,50,62].…”