Computational image sensors for on-sensor-compression

Hamamoto, Takayuki; Egi, Y.; Hatori, Mitsutoshi; Aizawa, Kiyoharu; Okubo, T.; Maruyama, Hirotaka; Fossum, Eric R.

doi:10.1109/mnnfs.1996.493806

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A High-Speed CMOS Image Sensor with On-chip Parallel Image Compression Circuits

Nishikawa

Kawahito

Furuta

et al. 2007

2007 IEEE Custom Integrated Circuits Conference

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This paper presents a high-speed CMOS image sensor with on-chip parallel image compression circuits. The chip consists of a pixel array, an A/D converter array with noise canceling function and an image compression processing element array and buffer memories. The image compression processing element is implemented with a 4×4 point Discreate Cosine Transform(DCT) and a modified zigzag scanner with 4 blocks. A prototype high-speed CMOS image sensor integrating the image compression circuits is implemented based on 1-poly 5-metal 0.25-µm CMOS technology. Image encoding using the implemented parallel image compression circuits to the image captured by the high-speed image sensor is successfully performed at 3,000[frame/s].

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