The CMOS imager architecture implements ∆Σ-modulated Haar wavelet image compression on the focal plane in real time. The active pixel array is integrated with a bank of column-parallel first-order incremental oversampling analogto-digital converters (ADCs). Each ADC performs column-wise distributed focal-plane sampling and concurrent signed weighted average quantization, realizing a one-dimensional spatial Haar wavelet transform. A digital delay and adder loop performs spatial accumulation over multiple adjacent ADC outputs. This amounts to computing a two-dimensional Haar wavelet transform, with no overhead in time and negligent overhead in area compared to a baseline digital imager architecture. The architecture is experimentally validated on a 0.35 micron CMOS prototype containing a bank of first-order incremental oversampling ADCs computing Haar wavelet transform on an emulated pixel array output. The architecture yields simulated computational throughput of 1.4 GMACS with SVGA imager resolution at 30 frames per second.
We present an algorithmic AZY-modulated FIR filter D Digital which computes digital convolution of a continuous-time analog A ADO FIR D input signal with a programmable digital impulse response. Selective sampling of the input signal controlled by unary-encoded FIR (a) coefficients yields bit-serial analog-digital multiplication. A AZ\-Analog A modulated analog-to-digital converter samples a time-varying A FIR A ADC D input at multiple instances in time generating a quantized version Processor of the average of all weighted samples. Computational throughput (b) of an arbitrary FIR filter is maximized by algorithmic resampling of the modulation residue to obtain higher resolution bits. This AM-Modulated yields a bit resolution linear in the number of conversion cycles. A FIR D A 1.9mm x 1.3mm 128-channel FIR filter integrated prototype Processor was fabricated in a 0.35 ,um CMOS technology. It yields a (c) computational throughput of up to 3.8 GMACS, with computational quantization time, power dissipation, and integration area iomparable qua ation thse, inpaonvendistionalosamintegranal-tio-a Fig. 1. FIR filter architectures with (a) a digital processor, (b) an analog comparable to those in a conventional oversampling analog-to-poesr n c Emdltdpoesr diia covrtr processor, and (c) a AZE-modulated processor.digital converter.
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