A High-Speed CMOS Image Sensor with On-chip Parallel Image Compression Circuits

Nishikawa, Yasuko; Kawahito, Shoji; Furuta, Mamoru; Tamura, Tamotsu

doi:10.1109/cicc.2007.4405857

Cited by 23 publications

(10 citation statements)

References 10 publications

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“…Generally, in high-speed vision systems, the challenges of insufficient bandwidth and storage are increasingly severe and gradually become the bottlenecks. In practice, image compression is widely considered as an effective approach to relieving the above-mentioned problems since it can reduce the data to a more manageable level before the image sequences are transmitted [6,7].…”

Section: Introductionmentioning

confidence: 99%

A Hardware-Efficient Vector Quantizer Based on Self-Organizing Map for High-Speed Image Compression

et al. 2017

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This paper presents a compact vector quantizer based on the self-organizing map (SOM), which can fulfill the data compression task for high-speed image sequence. In this vector quantizer, we solve the most severe computational demands in the codebook learning mode and the image encoding mode by a reconfigurable complete-binary-adder-tree (RCBAT), where the arithmetic units are thoroughly reused. In this way, the hardware efficiency of our proposed vector quantizer is greatly improved. In addition, by distributing the codebook into the multi-parallel processing sub-blocks, our design obtains a high compression speed successfully. Furthermore, a mechanism of partial vector-component storage (PVCS) is adopted to make the compression ratio adjustable. Finally, the proposed vector quantizer has been implemented on the field programmable gate array (FPGA). The experimental results indicate that it respectively achieves a compression speed of 500 frames/s and a million connections per second (MCPS) of 28,494 (compression ratio is 64) when working at 79.8 MHz. Besides, compared with the previous scheme, our proposed quantizer achieves a reduction of 8% in hardware usage and an increase of 33% in compression speed. This means the proposed quantizer is hardware-efficient and can be used for high-speed image compression.

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Section: Introductionmentioning

confidence: 99%

A Hardware-Efficient Vector Quantizer Based on Self-Organizing Map for High-Speed Image Compression

et al. 2017

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“…Reference [60] reported a high-speed (>1000 fps) CMOS image sensor with a resolution of 256 × 256 integrated together with a DCT processor. In order to achieve a highprocessing speed, global electronic shutters are implemented with pixel-level sample-hold function unit as illustrated in Figure 6.…”

Section: Efficiency Of the Image-sensor Array Readoutmentioning

confidence: 99%

“…Off-array processor Figure 6: Architecture of high-speed CMOS image sensor with a resolution of 256 × 256 integrated a DCT processor. Sample-hold function unit is implemented in pixel-level circuit for the global electronic shutters so as to enhance the speed of the overall system as proposed in [60].…”

Section: Journal Of Sensorsmentioning

confidence: 99%

CMOS Image Sensor with On-Chip Image Compression: A Review and Performance Analysis

Zhang

Bermak

2010

Journal of Sensors

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Demand for high-resolution, low-power sensing devices with integrated image processing capabilities, especially compression capability, is increasing. CMOS technology enables the integration of image sensing and image processing, making it possible to improve the overall system performance. This paper reviews the current state of the art in CMOS image sensors featuring on-chip image compression. Firstly, typical sensing systems consisting of separate image-capturing unit and image-compression processing unit are reviewed, followed by systems that integrate focal-plane compression. The paper also provides a thorough review of a new design paradigm, in which image compression is performed during the image-capture phase prior to storage, referred to as compressive acquisition. High-performance sensor systems reported in recent years are also introduced. Performance analysis and comparison of the reported designs using different design paradigm are presented at the end.

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“…Moreover, the high-speed clock could couple to the analog sensor circuits [5]. Hence, more frequently, array sensors are organized in columns and quantized by ADC arrays ( [4], [6]- [11]). …”

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confidence: 99%

“…However, slope ADCs have high over-sampling clock ratio. For sensors sampled at 100 kS/s with 10-b resolution or higher, successive-approximation register ADCs (SAR ADCs) [8], [9] and cyclic ADCs [10], [11] are normally designed. Similar to pipelined ADCs, cyclic ADCs require high-gain and high-speed operational amplifiers (OPAMPS) for good linearity and short settling time ( [12], [13]).…”

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confidence: 99%

Digitally Calibrated 768-kS/s 10-b Minimum-Size SAR ADC Array With Dithering

Liu

Yuan

2012

IEEE J. Solid-State Circuits

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Array sensors require a high-performance analog-todigital converter (ADC) array with small area and low power. Successive-approximation register (SAR) ADC has good potential for ADC array due to its simple analog circuits. However, SAR ADCs with 10-b resolution and higher normally need a large capacitor array due to the stringent matching requirement. The large capacitor array also limits the ADC dynamic performance. The capacitor mismatch has been compensated by analog calibration techniques. In this work, a novel digital calibration method is developed for SAR ADC based on dithering. With dithering, weights of most significant bit (MSB) capacitors can be measured accurately so that very small capacitors can be used in the SAR ADC due to the relaxed matching requirement. A modified bit-cycling procedure is developed to avoid the code gaps caused by capacitor dithering. This calibration technique requires no analog calibration overhead and simple digital decoders. The technique is implemented in an ADC array design including 256 SAR ADCs for a high-speed CMOS imaging sensor in a 0.18-m CMOS process. The 10-b SAR ADC is designed with the minimum capacitor array size in the process. A single SAR ADC only occupies15 m 710 m. Sampling at 768 kS/s, peak DNL and peak INL of the original ADCs averaged across the array are 0.82 least significant bit (LSB) and 3.85 LSB, respectively. For a signal close to the Nyquist frequency, original ADCs have 7.96-b average ENOB. After calibration with dithering, ADCs have 0.55-LSB peak DNL and 0.77-LSB peak INL averaged across the array. The average ENOB improves to 9.83 b. Compared with the benchmark 10-b SAR ADCs, this design is the most area-efficient design. In this work, the calibration decoders are implemented off-chip. With a sample-and-hold amplifier, the calibration method can run in the background.Index Terms-ADC array, analog-to-digital converter (ADC), digital calibration, dithering, successive-approximation register (SAR).

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A High-Speed CMOS Image Sensor with On-chip Parallel Image Compression Circuits

Cited by 23 publications

References 10 publications

A Hardware-Efficient Vector Quantizer Based on Self-Organizing Map for High-Speed Image Compression

A Hardware-Efficient Vector Quantizer Based on Self-Organizing Map for High-Speed Image Compression

CMOS Image Sensor with On-Chip Image Compression: A Review and Performance Analysis

Digitally Calibrated 768-kS/s 10-b Minimum-Size SAR ADC Array With Dithering

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