Comprehensive Understanding of Electron and Hole Mobility Limited by Surface Roughness Scattering in Pure Oxides and Oxynitrides Based on Correlation Function of Surface Roughness

Ishihara, T.; Matsuzawa, K.; Takayanagi, Motowo; Takagi, Shinichi

doi:10.1143/jjap.41.2353

Cited by 27 publications

(17 citation statements)

References 11 publications

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“…SRS limited mobility (μ SRS ) is extracted by line fit to μ-Ns curve at high Ns region and expressed by following expression, μ SRS = αxNs β . Changes of α and β mainly correspond to changes of amplitude and distribution of roughness (or surface potential fluctuation), respectively [10,14,15] . Figure 10 shows Δμ SRS as a function of Ns.…”

Section: T Shift and Mobility Degradationmentioning

confidence: 99%

Intrinsic correlation between mobility reduction and V<inf>t</inf> shift due to interface dipole modulation in HfSiON/SiO<inf>2</inf> stack by La or Al addition

Tatsumura

Ishihara

Inumiya

et al. 2008

2008 IEEE International Electron Devices Meeting

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Intrinsic correlation between mobility reduction by remote Coulomb scattering (RCS) and threshold voltage shift (ΔV t ), both of which are induced by interface dipole modulation at high-k/SiO 2 interface, is investigated. Three types of dipole modulation are examined; Al addition, La addition, and changing quality of interfacial SiO 2 layer. Extrinsic scattering components due to increases of interface state and surface roughness are extracted and separated. It is found that RCS due to interface dipole modulation by Al addition increases with increasing ΔV t , while that by La addition is constant, independent of ΔV t . Inevitability of additional scattering for ΔV t is discussed based on two different models for dipole formation mechanisms. IntroductionAggressive MOSFET device scaling requires a metal gate (MG)/high-k insulator (HK) gate stack [1] . Achieving suitable threshold voltage (V t ) for CMOS is one of the biggest issues for introduction of MG/HK stack, especially in production by gate-first process. Recently, the presence of energy offset at the high-k/SiO 2 interface is evidenced [2][3][4] , which is attributed to interfacial dipole layer. V t control technique by modulation of the interface dipole with adding atoms has been developed for CMOS integration. La [2,[5][6][7][8] and Al [3,4,9] are widely known to be effective for lowering V t of nMOS and pMOS, respectively. V t shift (ΔV t ) of several hundred mV due to interface dipole modulation corresponds to formation of charges (negative and positive) of larger than 10 13 cm -2 at the high-k/interfacial layer (IL) interface, which may affect channel mobility (μ) by remote Coulomb scattering (RCS) mechanism [10] . From observation of strong correlation between μ reduction and ΔV t , Ota et.al. [11] proposed a model that interface dipole scattering governs μ of high-k MOSFET. According to this model, tradeoff relation between μ reduction and ΔV t is inevitable. However, there are several reports showing an unaffected μ for V t shifted device [7,8] . It is of great importance to clarify intrinsic correlation between μ reduction and ΔV t after correcting μ reduction by extrinsic effects depending on processes.In this paper, we systematically investigate quantitative correlation between μ reduction and ΔV t . Three types of V t shifts are examined; Al addition, La addition, and changing quality of IL. Extrinsic scattering components by increases of interface state and surface roughness are experimentally

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Section: T Shift and Mobility Degradationmentioning

confidence: 99%

Intrinsic correlation between mobility reduction and V<inf>t</inf> shift due to interface dipole modulation in HfSiON/SiO<inf>2</inf> stack by La or Al addition

Tatsumura

Ishihara

Inumiya

et al. 2008

2008 IEEE International Electron Devices Meeting

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“…13 In order to describe the mobility of both electrons and holes, alternative expressions have been proposed both in real and reciprocal space. 14,15 These alternative expressions include an additional exponential parameter n, which for specific values reduce to the Gaussian and exponential models. No physical meaning has been given to this exponential parameter.…”

Section: Introductionmentioning

confidence: 99%

“…No physical meaning has been given to this exponential parameter. Isihara et al 14 studied the silicon interface with pure silicon dioxide (SiO 2 ) and with oxynitrides (SiON x ). They found that different values of the exponential parameter n were needed to successfully describe the roughness of both interfaces.…”

Section: Introductionmentioning

confidence: 99%

“…They found that different values of the exponential parameter n were needed to successfully describe the roughness of both interfaces. 14 To date, a) there has been no conclusive study of the relation between the surface roughness exponential parameter n with strain. The relation between the surface roughness exponential parameter n and the different surface models, including the Gaussian and exponential forms, remains poorly understood.…”

Section: Introductionmentioning

confidence: 99%

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Roughness analysis in strained silicon-on-insulator wires and films

Ureña

Olsen

Escobedo-Cousin

et al. 2014

Journal of Applied Physics

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Articles you may be interested inThe effect of surface roughness scattering on hole mobility in double gate silicon-on-insulator devices Strained silicon is used to enhance performance in state-of-the-art CMOS. Under device operating conditions, the effect of strain is to reduce the carrier scattering at the channel by a smoother semiconductor surface. This has never been completely understood. This paper gives first evidence of the variation in surface roughness under realistic strained conditions. At the nanoscale, the SiO 2 / Si interface roughness is dependent on the scale of observation (self-affinity). To date, there is no experimental study of the SiO 2 /Si interface roughness scaling with strain. This work presents the effect of uniaxial and biaxial strains on the surface roughness of strained silicon-on-insulator films and wires using atomic force microscopy. Levels of strain ranging from 0% to 2.3%, encompassing those used in present CMOS devices have been investigated. It is shown that the silicon surface is affected by uniaxial and biaxial strains differently. Three surface roughness parameters have been analyzed: root mean square roughness, correlation length, and the Hurst exponent, which is used to describe the scaling behavior of a self-affine surface. The results show that the root mean square roughness decreases (up to $40%) with increasing tensile strain, whereas the correlation length increases (up to $63 nm/%) with increasing tensile strain. The Hurst exponent also varies with strain and with the undulation wavelength regime (between $0.8 and 0.2). This dependency explains why some models used to determine the carrier mobility from experiments fit the data better with a Gaussian form, whereas other models fit the data better with an exponential form. V C 2014 AIP Publishing LLC. [http://dx.

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“…The N sub are 2x10 17 , 7x10 17 , and 2x10 18 cm -3 . In high-E eff region, μ of SiON is higher than SiO 2 universal μ due to modulation of surface roughness scattering (SRS) by nitrogen [13] . μ of high-k MISFETs degrades as compared to the SiO 2 MISFET (except for very high-E eff region) due to high-k inherent scattering such as remote Coulomb scattering (RCS) or remote phonon scattering [14] .…”

mentioning

confidence: 99%

Correlation between low-field mobility and high-field carrier velocity in quasi-ballistic-transport MISFETS scaled down to L<inf>g</inf>=30 nm

Tatsumura

Goto

Kawanaka

et al. 2009

2009 IEEE International Electron Devices Meeting (IEDM)

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Mobility (μ) and L g dependence of high-field velocity (v) is systematically investigated. A wide variety of μ characteristics are realized with various gate dielectrics of SiO 2 , SiON, HfLaSiON, and HfLaAlSiON. At L g =30nm, the sensitivities of v to μ and scaling in L g , (δv/v)/(δμ/μ) and (δv/v)/(δL g /L g ), are 0.43 and -0.45, respectively: in quasi-ballistic transport regime, μ and scaling in L g still play an important role on I on improvement with v enhancement. High-k MISFETs do not show any particular v degradation in high-energy carrier transport. μ-T inv characteristics of MG/high-k gate-stacks required for 22nm-node and beyond is discussed based on the experimental data for μ and L g dependence of v.Introduction For modern deeply-scaled MISFETs, precise understanding of correlation between low-field mobility (μ) and high-field carrier velocity (v), which is more directly related to on-current (I on ), becomes more and more important [1][2][3][4][5] (Fig. 1). This is because μ is a key engineering factor for the modern MISFETs: severe μ-T inv tradeoff relation has been commonly observed in sub-1.0nm-EOT MG/high-k stacks required for 22nm-node and beyond [6,7] . On the other hand, it is possible to improve μ by strained Si technique at the expenses of process and/or area costs.The determination mechanism of v is dependent on the gate length (L g ) [8] . In long-channel MISFETs, μ is the solely important factor in determining v. As velocity saturation phenomenon begins to occur, μ dependence of v becomes weaker [3] . In quasi-ballistic transport regime, under which modern MISFETs are considered to be operating [9] , μ could play an important role because backscattering ratio for carriers injected from source to channel is related to μ [1,10] . And, ultimately, in full-ballistic regime μ loses its meaning because v is determined solely by injection velocity [11] . While there are intensive theoretical and simulation studies, quantitative experimental data for μ dependence of v has not been sufficient in quasi-ballistic transport regime. In addition, high-k inherent optical phonons [12] might affect the high-energy carrier transport by inelastic scattering process. But the effects have not been fully clarified.In this work, we systematically investigate μ and L g dependence of v in wide ranges of μ and L g and clarify the sensitivities of v to μ and scaling in L g , (δv/v)/(δμ/μ) and (δv/v)/ (δL g /L g ), in quasi-ballistic transport regime. As L g decreases, the sensitivities of v to μ and scaling in L g should decrease from their long-channel values of 1 and -1 (v is proportional to μ and inversely proportional to L g ) and ultimately approach to 0 (v is independent of μ and L g ). MISFETs with various gate dielectrics (SiO 2 , SiON, HfLaSiON, and HfLaAlSiON) and various substrate impurity concentrations (N sub ) are prepared to realize a wide variety of μ characteristics and to examine the particularity of high-k MISFETs in high-energy carrier transport.Strained Si technique is not used. μ-T inv chara...

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Comprehensive Understanding of Electron and Hole Mobility Limited by Surface Roughness Scattering in Pure Oxides and Oxynitrides Based on Correlation Function of Surface Roughness

Cited by 27 publications

References 11 publications

Intrinsic correlation between mobility reduction and V<inf>t</inf> shift due to interface dipole modulation in HfSiON/SiO<inf>2</inf> stack by La or Al addition

Intrinsic correlation between mobility reduction and V<inf>t</inf> shift due to interface dipole modulation in HfSiON/SiO<inf>2</inf> stack by La or Al addition

Roughness analysis in strained silicon-on-insulator wires and films

Correlation between low-field mobility and high-field carrier velocity in quasi-ballistic-transport MISFETS scaled down to L<inf>g</inf>=30 nm

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