Comprehensive study of substrate noise isolation for mixed-signal circuits

To, Kun-Hin; Welch, P.; Bharatan, S.; Lehning, H.; Huynh, Trong‐Phuoc; Thoma, R.; Monk, David J.; Huang, Wenjie; Ilderem, V.

doi:10.1109/iedm.2001.979559

Cited by 31 publications

(14 citation statements)

References 7 publications

(2 reference statements)

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“…Also, some reports [1,7] have noted that the supply noise dominates substrate noise. Accordingly, dedicated substrate bias and guard rings have been developed and demonstrated to be highly effective in reducing substrate noise for digital and mixed-signal circuit [8][9][10].…”

Section: Introductionmentioning

confidence: 99%

Power and Substrate Noise Tolerance of Configurable Embedded Memories in SoC

Chang

Wen

2005

J VLSI Sign Process Syst Sign Image Video Technol

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When subject to various power and substrate noise, configurable embedded memories in multimedia SoCs are importantly affected with pattern-dependant soft failures. This work investigates the effects of such failures on memory cells, arrays and circuit design. The ground bounce reduces the memory cell current more than the supply voltage drop or the substrate bias dip. A noise track-and-filter (NTAF) architecture, which is a self-timed architecture with specific layout patterns, is presented to provide the required timing relaxation, while minimizing the speed degradation. This NTAF method provides greater noise tolerance and design for manufacturing (DFM) capability. Configurable embedded SRAM and ROM in 0.18 µm CMOS process are studied.

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Section: Introductionmentioning

confidence: 99%

Power and Substrate Noise Tolerance of Configurable Embedded Memories in SoC

Chang

Wen

2005

J VLSI Sign Process Syst Sign Image Video Technol

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“…In recent processes, a triple-well structure, which involves additional fabrication cost, is often used for body biasing in high-performance and low-power designs [7] noise reduction in mixed systems-on-chip designs [8]. In addition, the PN junction capacitance associated with triplewell structures works as a decoupling capacitance (decap) and contributes to mitigation of the power supply noise.…”

Section: Introductionmentioning

confidence: 99%

“…In addition, the PN junction capacitance associated with triplewell structures works as a decoupling capacitance (decap) and contributes to mitigation of the power supply noise. Although substrate noise reduction in the triple-well structure has been actively discussed [8], solid measurements of supply noise reduction by the triple-well structure have not been reported as far as the authors know. In addition, isolation from the p-substrate by a triple-well structure immunizes the p-substrate effect on the power supply.…”

Section: Introductionmentioning

confidence: 99%

Supply Noise Suppression by Triple-Well Structure

Ogasahara

Hashimoto

Kanamoto

et al. 2013

IEEE Trans. VLSI Syst.

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Abstract-This brief discusses the impact of twin-and triplewell structures on power supply noise, and a substrate model for simulating the power supply noise. We observed V ss noise reduction by the resistive network of the p-substrate and V dd noise reduction by the junction capacitance of a triple-well structure on a 90-nm test chip. Measurement results also showed that the total noise reduction of a triple-well structure is superior to that of a twin-well structure. The measurement results correlate well with the results obtained from the power supply noise simulation using a hierarchical resistive mesh model. Our simulation-based verification indicates that in common CMOS design, a triplewell structure can reduce the power supply drop by 10%-40% or the decoupling capacitance area by 5%-10%. We also verified that supply drop sensitivity to variation of the well junction capacitance is sufficiently small and that supply noise reduction using a triple-well structure is robust to process variation.Index Terms-Circuit noise, noise measurement, substrate.

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“…Also, there are reports [4,11] pointing out that the power supply noise is a dominant source for substrate noise. Therefore, dedicated substrate bias and guard ring have been proposed and proven to be very effective in substrate noise reduction for digital and mixed-signal circuit [12][13][14].…”

Section: Introductionmentioning

confidence: 99%