Supply Noise Suppression by Triple-Well Structure

Ogasahara, Yasuhiro; Hashimoto, Masanori; Kanamoto, Toshiki; Onoye, Takao

doi:10.1109/tvlsi.2012.2192458

Cited by 13 publications

(2 citation statements)

References 15 publications

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“…With a p-substrate triple-well process, an additional deep n-well is diffused to isolate the p-well diffusions of the individual MOSFETs from the common p-substrate, allowing an independent body terminal connection for each MOSFET. The triple-well structure yields better noise characteristics as compared with the traditional twin-well structure, without increasing the gate leakage [30]. Alternatively, the triple-well structure, exhibits additional fabrication costs and area overheads due to requirements on the minimum width and spacing of deep n-wells.…”

Section: Fabrication Costsmentioning

confidence: 99%

A Single-MOSFET Analog High Resolution-Targeted (SMART) Multiplier for Machine Learning Classification

Kenarangi

Partin-Vaisband

2021

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Mixed-signal machine-learning classification has recently been demonstrated as an efficient alternative for classification with power expensive digital circuits. In this paper, a single-MOSFET analog multiplier is proposed for classifying high-dimensional input data into multi-class output space with less power and higher accuracy than state-of-the-art mixed-signal linear classifiers. A high-resolution (i.e., multi-bit) multiplication is facilitated within a single-MOSFET by feeding the features and feature weights into, respectively, the body and gate inputs. Highresolution classifier that considers the decisions of the individual predictors is designed at 180 nm technology node and operates at 100 MHz in near/subthreshold region. To evaluate the performance of the classifier, a reduced MNIST dataset is generated by downsampling the MNIST digit images from 784 features to 48 features. The system is simulated across a wide range of PVT variations, exhibiting average accuracy of 92% (2% improvement over state-of-the-art), energy consumption of 67.3 pJ per classification (over 8 times lower than state-of-the-art classifiers), area of 27,570 µm 2 per binary classifier, and a stable response under PVT variations. Finally, to provide ground for future work on ultra-low-power deep and convolutional networks, scalability and robustness of the proposed multiplier is evaluated with a convolutional neural network on CIFAR-10. Similar classification accuracy with digital and SMART hardware has been observed. All the code and simulation files are available at an online public GitHub repository, https://github.com/faridken/SMART-Multiplier-for-ML.

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Section: Fabrication Costsmentioning

confidence: 99%

A Single-MOSFET Analog High Resolution-Targeted (SMART) Multiplier for Machine Learning Classification

Kenarangi

Partin-Vaisband

2021

IEEE J. Emerg. Sel. Topics Circuits Syst.

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“…In a p-substrate triple-well process, an additional deep n-well is used to isolate the p-well of each MOSFET from the p-substrate, allowing an independent body terminal connection for each MOSFET. The triple-well structure has been demonstrated to provide better noise characteristics as compared with the traditional twin-well structure, without increasing the gate leakage [29]. Alternatively, the triple-well structure, exhibits additional fabrication costs and area overheads that needs to be considered.…”

Section: Fabrication Costsmentioning

confidence: 99%

A Single-MOSFET MAC for Confidence and Resolution (CORE) Driven Machine Learning Classification

Kenarangi¹,

Partin-Vaisband²

2019

Preprint

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Mixed-signal machine-learning classification has recently been demonstrated as an efficient alternative for classification with power expensive digital circuits. In this paper, a high-COnfidence high-REsolution (CORE) mixed-signal classifier is proposed for classifying high-dimensional input data into multiclass output space with less power and area than state-of-the-art classifiers. A high-resolution multiplication is facilitated within a single-MOSFET by feeding the features and feature weights into, respectively, the body and gate inputs. High-resolution classifier that considers the confidence of the individual predictors is designed at 45 nm technology node and operates at 100 MHz in subthreshold region. To evaluate the performance of the classifier, a reduced MNIST dataset is generated by downsampling the MNIST digit images from 28 × 28 features to 9 × 9 features. The system is simulated across a wide range of PVT variations, exhibiting nominal accuracy of 90%, energy consumption of 6.2 pJ per classification (over 45 times lower than state-of-the-art classifiers), area of 2,179 µm 2 (over 7.3 times lower than state-ofthe-art classifiers), and a stable response under PVT variations.

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Integrated Silicon Photodetectors

Zimmermann¹

2018

Silicon Optoelectronic Integrated Circuits

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Supply Noise Suppression by Triple-Well Structure

Cited by 13 publications

References 15 publications

A Single-MOSFET Analog High Resolution-Targeted (SMART) Multiplier for Machine Learning Classification

A Single-MOSFET Analog High Resolution-Targeted (SMART) Multiplier for Machine Learning Classification

A Single-MOSFET MAC for Confidence and Resolution (CORE) Driven Machine Learning Classification

Integrated Silicon Photodetectors

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