Comprehensive extensibility of 20nm low power/high performance technology platform featuring scalable high-k/metal gate planar transistors with reduced design corner

Fukutome, H.; Cheon, Kang Woo; Kim, J. P.; Kim, J. C.; Lee, J. G.; Cha, Sungyong; Roh, Ukjin; Kwon, Sung-Joo; Sohn, Dong Kyun; Maeda, S.

doi:10.1109/iedm.2012.6478973

Cited by 7 publications

(3 citation statements)

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“…Fully-depleted (FD) planar SOI transistors are also introduced by ST at 28nm CMOS [17] to reduce the statistical variability. Many technology providers, however, continue to rely on conventional bulk transistors at the 20 nm CMOS technology generation planed for early introduction in 2013 [18].…”

Section: Introductionmentioning

confidence: 99%

Geometry, Temperature, and Body Bias Dependence of Statistical Variability in 20-nm Bulk CMOS Technology: A Comprehensive Simulation Analysis

Wang

Adamu-Lema

Cheng

et al. 2013

IEEE Trans. Electron Devices

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Abstract-Conventional bulk CMOS, which is arguably most vulnerable to statistical variability, has been the workhorse of the electronic industry for more than three decades. In this paper, the dependence of the statistical variability of key figures of merit on gate geometry, temperature and body bias in 25nm gate-length MOSFETs, representative for the 20nm CMOS technology generation, are systematically investigated using 3D statistical simulations. The impact of all relevant sources of statistical variability is taken into account. The geometry dependence of the threshold voltage dispersion (and indeed the dispersion of other key transistor figures of merit) does not necessarily follow the Pelgrom's law due to the complex non-uniform channel doping and the interplay of different statistical-variability sources. The DIBL variation for example follows a log-normal distribution. The temperature significantly affects the magnitudes of threshold-voltage, sub-threshold slope, on/off currents and the corresponding statistical distributions. Reverse body bias increases the threshold voltage and its fluctuation while forward body bias reduces both of them.

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Section: Introductionmentioning

confidence: 99%

Geometry, Temperature, and Body Bias Dependence of Statistical Variability in 20-nm Bulk CMOS Technology: A Comprehensive Simulation Analysis

Wang

Adamu-Lema

Cheng

et al. 2013

IEEE Trans. Electron Devices

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“…S TATISTICAL variability, associated with the discreteness of charge and granularity of matter, has become a maker or a breaker of contemporary and future CMOS technology generations [1]- [7]. The use of technology computer-aided design (TCAD) has been demonstrated to be essential for the understanding, forecast, and control of statistical variability in the technology development and the optimization process [8]- [11].…”

Section: Introductionmentioning

confidence: 99%

A Mobility Correction Approach for Overcoming Artifacts in Atomistic Drift-Diffusion Simulation of Nano-MOSFETs

Amoroso

Adamu-Lema

Brown

et al. 2015

IEEE Trans. Electron Devices

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A comprehensive statistical investigation of the increase in resistance associated with charge trapping in atomistic simulations is presented. A wide range of doping densities and mesh spacing are considered for both classical and quantum formalisms. A doping-dependent correction factor to modify the mobility model for the atomistic simulations is proposed to suppress the error related to the fictitious charge trapping. The validity of the new mobility model is tested in the statistical simulations of the transistors corresponding to 20-nm bulk CMOS and 14-nm FinFET transistors.

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“…A three--dimensional multi--gate FinFET architecture has been adopted by Intel at the 22 nm node [1], and a fully--depleted SOI MOSFETs have been introduced by ST Microelectronics at the 28 nm node [2]. However, technology considerations and cost still render bulk planar MOSFETs an attractive technology for many markets [3]. All FET architectures, including bulk planar MOSFETs, are subject to unavoidable statistical variability and reliability issues resulting from the discreteness of charge and granularity of matter-issues which have become a critical concern for device scaling and power dissipation, already affecting adversely the SRAM yield [4].…”

Section: Introductionmentioning

confidence: 99%

Drain bias effects on statistical variability and reliability and related subthreshold variability in 20-nm bulk planar MOSFETs

Wang

Brown

Cheng

et al. 2014

Solid-State Electronics

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Abstract-Statistical variability and reliability due to random discrete dopants (RDD), gate line edge roughness (LER), metal gate granularity and N/PBIT associated random charge trapping has limited the progressive scaling of bulk planar MOSFETs beyond the 20--nm technology node. In this paper, their impacts on device figures of merit are studied through comprehensive 3--D simulation. It is found that raised drain--bias can exacerbate threshold--voltage fluctuations, mainly due to LER and RDD. Subthreshold slope (SS) variations resulting from each variation source is studied: RDD and LER generate most of the SS variation and are primarily responsible for its skew. Drain induced barrier lowering (DIBL) is examined against each intrinsic variation source, and RDD and LER are found to cause most of the DIBL variability. The correlation of DIBL with threshold--voltage is fully analysed with respect to each source of statistical variability and reliability. Except for LER, all major sources of variability exhibit de--correlation of DIBL against threshold--voltage.

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Comprehensive extensibility of 20nm low power/high performance technology platform featuring scalable high-k/metal gate planar transistors with reduced design corner

Cited by 7 publications

References 0 publications

Geometry, Temperature, and Body Bias Dependence of Statistical Variability in 20-nm Bulk CMOS Technology: A Comprehensive Simulation Analysis

Geometry, Temperature, and Body Bias Dependence of Statistical Variability in 20-nm Bulk CMOS Technology: A Comprehensive Simulation Analysis

A Mobility Correction Approach for Overcoming Artifacts in Atomistic Drift-Diffusion Simulation of Nano-MOSFETs

Drain bias effects on statistical variability and reliability and related subthreshold variability in 20-nm bulk planar MOSFETs

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