Comparison of Electrical Characteristics of 28 Nm Bulk MOSFET and FDSOI MOSFET

Godara, Mehak; Madhu, Charu; Joshi, Garima

doi:10.1109/edkcon.2018.8770413

Cited by 4 publications

(6 citation statements)

References 19 publications

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“…To further expand CMOS technology beyond sub-45 nm, silicon-on-insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs) are a potential candidate to replace traditional planar MOSFETs. SOI technology has major advantages over planar MOS technology [1,2]. These benefits include low leakage current, faster switching speed, reduced subthreshold swing, better isolation, decreased latchup, and improved short-channel immunity [3].…”

Section: Introductionmentioning

confidence: 99%

A novel circular double-gate SOI MOSFET with raised source/drain

Sagar¹,

Maheshwaram²

2021

Semicond. Sci. Technol.

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In this paper, we report the performance of a novel circular double-gate (CDGT) silicon-on-insulator metal oxide semiconductor field effect transistor (MOSFET). We explore a variety of device configurations that are possible by making changes in the pad height in terms of a raised top, bottom, or top and bottom (both). The results demonstrate that the best device configuration is a raised both CDGT with an internal pad as a drain. For the above configuration, the impact of a junctionless mode is further analyzed and the optimum performance is obtained with a doping level of 1 × 1018 cm−3. The device exhibits good electrical characteristics, with an ON/OFF current ratio of 3.73 × 105, a near-ideal subthreshold slope of 66.9 mV dec−1, and a small drain-induced barrier lowering of ∼35 mV V−1. Among various circular MOSFETs, the CDGT device exhibits an optimum delay performance of 2 ps based on a two-stage inverter analysis.

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Section: Introductionmentioning

confidence: 99%

A novel circular double-gate SOI MOSFET with raised source/drain

Sagar¹,

Maheshwaram²

2021

Semicond. Sci. Technol.

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“…Equivalent oxide thickness (EOT) scaling with a high-k/metal gate approach has demonstrated the ability to show good performance using a gate-first process, as reported by Chen [ 19 ]. Many studies have been performed on the use of 28-nm planar bulk MOSFETs [ 20 ] to overcome scaling challenges from 65-nm to 28-nm [ 21 , 22 ]. The statistical optimization of the modelling of process parameters and the effects of process parameter variability for V th has been conducted by researchers [ 23 , 24 ].…”

Section: Introductionmentioning

confidence: 99%

A Feasible Alternative to FDSOI and FinFET: Optimization of W/La2O3/Si Planar PMOS with 14 nm Gate-Length

et al. 2021

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At the 90-nm node, the rate of transistor miniaturization slows down due to challenges in overcoming the increased leakage current (Ioff). The invention of high-k/metal gate technology at the 45-nm technology node was an enormous step forward in extending Moore’s Law. The need to satisfy performance requirements and to overcome the limitations of planar bulk transistor to scales below 22 nm led to the development of fully depleted silicon-on-insulator (FDSOI) and fin field-effect transistor (FinFET) technologies. The 28-nm wafer planar process is the most cost-effective, and scaling towards the sub-10 nm technology node involves the complex integration of new materials (Ge, III-V, graphene) and new device architectures. To date, planar transistors still command >50% of the transistor market and applications. This work aims to downscale a planar PMOS to a 14-nm gate length using La2O3 as the high-k dielectric material. The device was virtually fabricated and electrically characterized using SILVACO. Taguchi L9 and L27 were employed to study the process parameters’ variability and interaction effects to optimize the process parameters to achieve the required output. The results obtained from simulation using the SILVACO tool show good agreement with the nominal values of PMOS threshold voltage (Vth) of −0.289 V ± 12.7% and Ioff of less than 10−7 A/µm, as projected by the International Technology Roadmap for Semiconductors (ITRS). Careful control of SiO2 formation at the Si interface and rapid annealing processing are required to achieve La2O3 thermal stability at the target equivalent oxide thickness (EOT). The effects of process variations on Vth, Ion and Ioff were investigated. The improved voltage scaling resulting from the lower Vth value is associated with the increased Ioff due to the improved drain-induced barrier lowering as the gate length decreases. The performance of the 14-nm planar bulk PMOS is comparable to the performance of the FDSOI and FinFET technologies at the same gate length. The comparisons made with ITRS, the International Roadmap for Devices and Systems (IRDS), and the simulated and experimental data show good agreement and thus prove the validity of the developed model for PMOSs. Based on the results demonstrated, planar PMOSs could be a feasible alternative to FDSOI and FinFET in balancing the trade-off between performance and cost in the 14-nm process.

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“…Neste caso, o dispositivo é chamado de transistor SOI totalmente depletado (FD, do inglês, fully depleted) ou transistor SOI de camada fina. Estes dispositivos apresentam as características elétricas superiores em relação aos outros tipos de transistores SOI, tais como menor ocorrência de efeitos de canal curto (YOUNG,1989;GODARA et al, 2018), maior mobilidade dos portadores na região do canal (YOSHIMI,1989;MONSIEUR, 2014), menor variação da tensão de limiar com a temperatura (GROESENEKEN, 1990), redução do campo elétrico transversal (KISTLER, 1994), entre outras.…”

Section: Dispositivos Soi Totalmente Depletados (Fd Soi)unclassified

“…Devido à miniaturização dos dispositivos e consequentemente à redução do comprimento de canal, surgem efeitos indesejáveis, chamados de efeito de canal curto (YOUNG, 1989;GODARA et al, 2018). A redução do comprimento de canal faz com que as regiões de depleção de fonte e dreno tornem-se significativas em relação à região de depleção causada pela tensão aplicada à porta.…”

Section: Efeitos De Canal Curtounclassified

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Análise da mobilidade em transistores SOI de canal gradual visando simulações de circuitos

Silva¹

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The GC (Graded-Channel) SOI (Silicon-On-Insulator) MOSFET (Metal-OxideSemiconductor Field Effect Transistor) transistor is a SOI transistor whose channel is divided into two regions: a highly doped region and a lightly doped region. The reduction of the doping concentration in the channel region near the drain allows GC SOI transistors to present a series of advantages over the conventional uniformly doped transistor, showing better analog characteristics, such as higher current level, increased transconductance, reduction of drain conductance, which implies higher Early voltage, and higher breakdown voltage. The association of these characteristics shows that GC SOI MOSFET has great potential for applications in analog integrated circuits. One of the steps in the design of integrated circuits is the simulation of these circuits. To allow for reliable simulations, analytical models that describe the electronic devices are required. Although a proposed model has been presented for the GC SOI transistor, it is not implemented in commercial simulators. To circumvent this, some works demonstrate the simulation of GC transistors through the association of two uniformly doped SOI transistors with different doping concentrations and short-circuited gates. However, the adoption of this strategy makes necessary to use twice as many transistors in the simulated circuit. Additionally, the use of two transistors increases the source and drain capacitances of the intermediate point between the two devices. Aiming at simulating and designing analog circuits using a graded-channel structure, this work presents a study of the effective mobility of GC SOI transistors. The objective is to simulate the graded channel transistor using available models in commercial simulators for uniformly doped SOI transistors, by adjusting its parameters, which would became dependent on the lengths and doping concentrations of the two regions of the channel. This work demonstrates that using mobility parameters such as low field mobility (µ0), linear (?1) and quadratic (?2) degradation factors, extracted by Y-Function method and making adjustments to the PCLM parameter, included in the BSIM-SOI model and which is related to the channel modulation effect, it is possible to reproduce the behavior in the drain current (IDS) and transconductance (gm) curves as a function of the gate voltage (VGS) and in the drain current (IDS) and output conductance (gD) curves as a function of drain voltage (VDS) using a single uniformly doped SOI MOSFET transistor in a SPICE simulator. The results showed a maximum error of 5.26% and 10.34% in the drain current (IDS) and transconductance (gm) curves, respectively, as a function of the gate voltage (VGS) for low drain voltage (VDS) in GC transistors with channel length (L) of 1 µm and 2 µm. For high drain voltage (VDS), the errors obtained were 10.68% and 14.08% in the drain current (IDS) and transconductance (gm) curves, respectively, as a function of the gate voltage (VGS) for 2 µm GC transistors. The drain current curves (IDS) as a function of drain voltage (VDS) showed an error of less than 5.4% with overdrive voltage (VGT) ranging from 200mV to 600mV. The output conductance (gD) as a function of the drain voltage (VDS) was reproduced, showing a better approximation with the experimental data by adjusting the PCLM parameter. The best results were obtained for low overdrive voltage (VGT) in the saturation region. The adjustment of the PCLM parameter together with the mobility parameters, (µ0), (?1) and (?2), allowed simulating the behavior of the GC transistor with good approximation, which can make this an interesting approach for an initial step of analytical simulation of analog integrated circuits using the GC SOI MOSFET transistor

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Comparison of Electrical Characteristics of 28 Nm Bulk MOSFET and FDSOI MOSFET

Cited by 4 publications

References 19 publications

A novel circular double-gate SOI MOSFET with raised source/drain

A novel circular double-gate SOI MOSFET with raised source/drain

A Feasible Alternative to FDSOI and FinFET: Optimization of W/La2O3/Si Planar PMOS with 14 nm Gate-Length

Análise da mobilidade em transistores SOI de canal gradual visando simulações de circuitos

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