A novel circular double-gate SOI MOSFET with raised source/drain

Sagar, Kallepelli; Maheshwaram, Satish

doi:10.1088/1361-6641/abf0e6

Cited by 15 publications

(3 citation statements)

References 29 publications

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“…2, utilizes a self-aligned fabrication procedure. 28 To achieve high performance, the alternative wafer bonding technique 30 can be used in step (d) of the fabrication process. In this Fig.…”

Section: Device Structure Fabrication Processmentioning

confidence: 99%

“…26,27 A circular double gate transistor (CDGT) has recently been proposed, which provides better electrical performance than CGT at lower technology nodes. 28,29 With the advantages of both NSH-FETs and Circular geometry, in this work, a new idea called Circular Nanosheet FETs (C-NSFETs) is proposed at sub 10 nm channel length with an internal silicon pad as a drain. Further, we expand our work in terms of stacked C-NSFETs like 2 sheets, 3 sheets, and 4 sheets and compare their electrical performance for both N-type& P-type MOSFETs.…”

mentioning

confidence: 99%

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A Novel Vertically Stacked Circular Nanosheet FET for High-Performance Applications

Sagar

Maheshwaram

2022

ECS J. Solid State Sci. Technol.

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Nanosheet metal oxide semiconductor field effect transistors (MOSFETs) with circular layout geometry, i.e. circular nanosheet MOSFETs (C-NSFETs) were explored using fully calibrated TCAD for high-performance (HP) applications at 10 nm gate length. The DC parameters such as drive current (ION), leakage current (IOFF), ON/OFF current ratio, Subthreshold slope (SS), and Drain-induced-barrier lowering (DIBL) are extracted. Further, we analyzed the behavior of C-NSFETs by vertically stacking the number of sheets (2-sheet, 3-sheet, and 4-sheet) and named stacked circular nanosheet MOSFETs and also compared the variations of their DC FOMs (figures of merit), is observed that the device drive current level is further improving by stacking of multiple Nanosheets within the same foot-print. The drive current of the device with the stacking of 4 sheets has an improvement of ~ 4 times when compared to single sheet C-NSFET.

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Section: Device Structure Fabrication Processmentioning

confidence: 99%

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confidence: 99%

A Novel Vertically Stacked Circular Nanosheet FET for High-Performance Applications

Sagar

Maheshwaram

2022

ECS J. Solid State Sci. Technol.

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“…Uniform doping of 1 × 10 18 cm −3 is maintained throughout the silicon fin. 31 The length of the source and drain spacer is maintained as 11 nm to have better subthreshold characteristics. In order to obtain a certain degree of flexibility, the TiN metal gate with a mid-gap work function of 4.5 eV is considered to acquire a specific threshold voltage.…”

Section: Device Structure and Simulation Detailsmentioning

confidence: 99%

p-Type Trigate Junctionless Nanosheet MOSFET: Analog/RF, Linearity, and Circuit Analysis

Sreenivasulu

Narendar

2021

ECS J. Solid State Sci. Technol.

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Silicon (Si) nanosheet (NS) metal-oxide semiconductor field effect transistors (MOSFETs) are realized as an outstanding structure to obtain better area scaling and power performance compared to FinFETs. The Si NS MOSFETs provide high current drivability due to wider effective channel (W eff) and maintain better short channel performance. Here, the performance of junctionless (JL) SOI NS p-MOSFET is evaluated by invoking HfxTi1−xO2 gate stack to overcome adverse short channel effects (SCEs). The device performance is enhanced using various spacer dielectrics and the electrical characteristics are presented. Moreover, the effect of NS width variation on I ON/I OFF, SS, V th is presented and the analog/RF metrics of the device are evaluated. The power consumption, dynamic power, and static power analyses of NS MOSFET is presented with respect to the ITRS road map. Our investigation reveals that the device exhibits an I ON/I OFF ratio of more than ∼106 with NS widths of 10 to 30 nm, respectively. The device exhibits better performance (I ON) with higher NS widths and ensures potential towards high-performance applications. However, with an increase in NS widths the threshold voltage (V th) tends to downfall and leads to deterioration in subthreshold performance . With high-k spacer dielectric the device exhibits better static power consumption for the CMOS inverter. By careful control of NS width and effective usage of spacer dielectric ensures better p-MOSFET design for future technology nodes.

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Design insights into RF /analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications

Sreenivasulu

Narendar

2021

Int J RF Mic Comp-Aid Eng

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Multi-fin devices are the most reliable option for terahertz (THz) frequency applications at nano-regime. In this work impact of spacer engineering on multi-fin SOI FET performance is evaluated by invoking single low-k (Air), high-k (Si 3 N 4 , HfO 2 ), and hybrid dual-k (Air + Si 3 N 4 ) spacer in the underlap section at nano-regime. The simulation study reveals that the high-k (HfO 2 ) spacer gives a higher switching ratio (I ON /I OFF ) in the order of ~10 7 , subthreshold swing (SS) = 72 mV/dec, drain induced barrier lowering (DIBL) = 22.14 mV/V and quality factor (Q) = g m /SS = 0.16 μS-dec/mV. Furthermore, to measure the suitability of the device for high frequency applications various analog/RF parameters are studied. The high-k (HfO 2 ) spacer dominates DC and analog performance, whereas the low-k (Air) spacer dominates the RF domain with f T = 1.26 THz, GBW = 0.251 THz, TFP = 29 THz range, and with smaller intrinsic delays. Hybrid dual-k spacer (Air + Si 3 N 4 ) outperforms in terms of gain (A V ) and output resistance (R o ). The Air spacer exhibits lower dynamic power of 2.09 aJ/μm and power consumption of 1.04 aJ/μm. The linearity metrics for multi-fin SOI FET parameters like g m2 , g m3 , HD1, HD2, THD, and VIP2 are also studied. The Air spacer followed by hybrid spacer outperforms in linearity, and harmonic distortion components and ensures its potential for RF applications at nano-regime.

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A novel circular double-gate SOI MOSFET with raised source/drain

Cited by 15 publications

References 29 publications

A Novel Vertically Stacked Circular Nanosheet FET for High-Performance Applications

A Novel Vertically Stacked Circular Nanosheet FET for High-Performance Applications

p-Type Trigate Junctionless Nanosheet MOSFET: Analog/RF, Linearity, and Circuit Analysis

Design insights into RF /analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications

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