Comparative Performance Analysis of XOR-XNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design

Wairya, Subodh; Nagaria, R. K.; Tiwari, Sudarshan

doi:10.5121/vlsic.2012.3219

Cited by 36 publications

(16 citation statements)

References 32 publications

(25 reference statements)

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“…17,18 However, the major drawback of the domino dynamic logic is its excessive power dissipation due to switching activity and clock load. Domino dynamic logic's performance is also mainly a®ected by charge sharing and race problems.…”

Section: Previous Workmentioning

confidence: 99%

Dual Threshold Voltage Domino Adder Design With Pass Transistor Logic Using Standby Switch for Reducing Sub-Threshold Leakage Current

Yuan

2014

J CIRCUIT SYST COMP

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Standby switch can strongly turn o® all the high threshold voltage transistors, which enhances the e®ectiveness of a dual threshold voltage CMOS technology to reduce sub-threshold leakage current. Sub-threshold leakage currents are especially important in burst mode type integrated circuits where the system is in an idle mode in the majority of the time. The standby switch allows a domino system to enter and leave a low leakage standby mode within a single clock cycle. In addition, we combine domino dynamic logic with pass transistor XNOR and pass transistor NAND gates to achieve logic 1 output during its precharge phase without a®ecting circuits operation in its evaluation and standby phase. The required process for dual threshold voltage circuit con¯guration involves only one additional ion implant step to provide an extra threshold voltage. SPICE simulation for our proposed circuits is made using a 0.18 m CMOS processes from TSMC, with 10 fF capacitive loads in all output nodes, and parameters for typical process corner at 25 C. Layout is designed, wafer is fabricate and measured. The measurement results of fabricated chips are listed and verify that our designed 8-bit carry lookahead adders (CLAs) reduced power consumption and propagation delay time by more than 15% and around 20%, respectively, when compared with the prior work.

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Section: Previous Workmentioning

confidence: 99%

Dual Threshold Voltage Domino Adder Design With Pass Transistor Logic Using Standby Switch for Reducing Sub-Threshold Leakage Current

Yuan

2014

J CIRCUIT SYST COMP

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“…The majority of the power dissipated in CMOS VLSI circuits is by dynamic power dissipation which is the power dissipated during charging or discharging of the load capacitance of a given circuit [13]- [15]. PTL based 10T full adder design by using 4T XOR and 2T Mux has been shown in Fig.…”

Section: Fig 8: Ptl Full Adder Design By 2x1 Mux [13]mentioning

confidence: 99%

Area Efficient 1-Bit Comparator Design by using Hybridized Full Adder Module based on PTL and GDI Logic

Sharma¹,

Singh²,

Kajla³

2013

IJCA

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In this paper an area efficient 17T 1-bit hybrid comparator design has been presented by hybridizing PTL and GDI techniques. The proposed 1-bit comparator design consist of 9 NMOS and 8 PMOS. A PTL and GDI full adder module has been used which consume less area at 120 nm as compared with the previous full adder designs. The proposed Hybrid 1-bit comparator design is based on this area efficient 9T full adder module. To improve area and power efficiency a cascade implementation of XOR module has been avoided in the used full adder module. Full adder modules outputs have been used for the generation of three different output of 1-bit comparator designs. The proposed 1-bit comparator has been designed and simulated using DSCH 3.1 and Microwind 3.1 on 120nm. Also the simulation of layout and parametric analysis has been done for the proposed 1-bit comparator design. Power and current variation with respect to the supply voltage has been performed on BSIM-4 and LEVEL-3 on 120nm. Results show that area consumed by the proposed hybrid adder is 329.3µm 2 on 120nm technology. At 1.4V input supply voltage the proposed 1-bit hybrid comparator consume 0.367mW power at BSIM-4 and 0.411mW power at LEVEL-3 and 2.313mA current at BSIM-4 and 3.047mA current at LEVEL-3 model

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“…The emergence of semiconductor industry is driving the designers to strain for smaller silicon area, longer battery life, higher speed and dependability [1]. As the process technology flinches, the critical worries have arrived with increasing leakage power consumption.…”

Section: Introductionmentioning

confidence: 99%

Design and analysis of FINFET pass transistor based XOR and XNOR circuits at 45 nm technology

Yadav

Khandelwal

Akashe

2013

2013 International Conference on Control, Computing, Communication and Materials (ICCCCM)

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The conventional single-gate MOSFETs faces great challenges in scaling down of devices due to the severe shortchannel effects that reason an exponential gain in the leakage current. To minimize the short channel effect Double-gate FinFET can be used in place of conventional MOSFET circuits because of the self-alignment of the two gates. Design of XOR and XNOR circuits is suggested to improve the speed and power of these circuits and is basic building block of many arithmetic circuits. This paper compares and evaluates the performance of various designs of pass transistor based XOR and XNOR circuits. This paper demonstrates comparative performance study of high speed, low power and low voltage on XOR and XNOR digital circuit. The performances of XOR and XNOR circuits are based on CADANCE VIRTUOSO tool at 45 nm by applying voltage supply 0.7 voltages and the temperate is 27 0 C. Simulation results reveal low power, delay, power, delay product (PDP), average dynamic power consumption, energy delay product (EDP).

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Comparative Performance Analysis of XOR-XNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design

Cited by 36 publications

References 32 publications

Dual Threshold Voltage Domino Adder Design With Pass Transistor Logic Using Standby Switch for Reducing Sub-Threshold Leakage Current

Dual Threshold Voltage Domino Adder Design With Pass Transistor Logic Using Standby Switch for Reducing Sub-Threshold Leakage Current

Area Efficient 1-Bit Comparator Design by using Hybridized Full Adder Module based on PTL and GDI Logic

Design and analysis of FINFET pass transistor based XOR and XNOR circuits at 45 nm technology

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