Comparative Analysis of Process Variation Impact on Flip-Flop Power-Performance

Hansson, Maria; Alvandpour, Atila

doi:10.1109/iscas.2007.378775

Cited by 23 publications

(10 citation statements)

References 7 publications

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“…Differently from the study presented in [6], where the process variability impact was analyzed considering FF circuits conventionally optimized for minimum EDP, we performed a comparative analysis considering yield improved circuit structures. This paper is organized as follows.…”

Section: Figmentioning

confidence: 99%

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Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis

Lanuzza

Rose

Frustaci

et al. 2011

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation

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Abstract. Process variations cause unpredictability in speed and power characteristics of nanometer CMOS circuits impacting the timing and energy yields. In this paper, transistor reordering and dual-Vth techniques are evaluated regarding their efficiency in mitigating the impact of process variations on a set of pulsed flip-flops. It is shown that the conjunct use of the above mentioned techniques can improve delay, energy and EDP yields more than 1.98X, 1.62X and 1.99X times, respectively. The yield optimized flip-flop circuits are also comparatively analyzed to identify the best topologies.

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Section: Figmentioning

confidence: 99%

“…FFs targeted for high speed applications in energy-constrained environments are conventionally sized to optimize the energy-delay-product (EDP) [6]. However, due to random process variations, a large number of circuits might not meet the targeted EDP constraint.…”

Section: Introductionmentioning

confidence: 99%

Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis

Lanuzza

Rose

Frustaci

et al. 2011

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation

View full text Add to dashboard Cite

show abstract

“…Flip-flop is a data storage element. The operation of the flip-flops is done by its clock frequency [3]. When multistage FlipFlop is operated with respect to clock frequency, it processes with high clock switching activity and then increases time latency.…”

Section: Introductionmentioning

confidence: 99%

Design of Hybrid Pulsed FlipFlop Featuring Embedded logic

Karthika¹,

Jayanthy²

2014

IOSRJVSP

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“…Unfortunately, when applied to a set of static and dynamic FFs, non-negligible power and area overheads are experienced [6]. In [7], it is demonstrated that, when conventionally optimized for minimum power-delay-product (PDP), static FFs present the best tolerance to process uncertainties, whereas high-performance pulsed topologies are more sensitive to random process variability.…”

Section: Introductionmentioning

confidence: 99%

“…Comparative studies presented in [5][6][7][8][9] refer to circuits optimized without taking into account energy variability, which is a very important issue in leakage-dominated technologies [1]. Moreover, the process variability impact on local interconnects is neglected.…”

Section: Introductionmentioning

confidence: 99%