Design of Hybrid Pulsed FlipFlop Featuring Embedded logic

Karthika, N.; Jayanthy, S.

doi:10.9790/4200-04216874

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“…A comparison of the proposed flip-flop with theconventional flip-flops showed that it exhibits lower powerdissipation along with speed performances. [3]. Varuna RTV have designed Dual Dynamic Edge TriggeredLow Power Flip-Flop Featuring ELM where edge triggering isprovided by the NMOS.…”

Section: Previous Work Donementioning

confidence: 99%

Review Paper on Power Efficient Hybrid D-Flip Flop

Babu¹

2013

IJAREEIE

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ABSTRACT:In nanometer CMOS technologies leakage powerhas become a serious concern and is a very important issue in hardware and software VLSI design. The leakage powerincreases as technology is scaled down. Low power flip-flops play a vital role for the design of low-power digital systems. In thispaper several different flip flop topologies are analyzed andpower efficient flip flop method is proposed. This paper presentssurvey on low power hybrid dual dynamic flip flop (DDFF) andembedded logic module (DDFF-ELM) based on DDFF. Thissurvey concludes that ultra low leakage CMOS structure calledas sleepy stack inverter pair method which is efficient in leakagepower reduction for design of low power hybrid flip flop thusproviding circuit designer with new choice to handle leakagepower problem.

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Section: Previous Work Donementioning

confidence: 99%

Review Paper on Power Efficient Hybrid D-Flip Flop

Babu¹

2013

IJAREEIE

View full text Add to dashboard Cite

show abstract

Design of Hybrid Pulsed FlipFlop Featuring Embedded logic

Cited by 1 publication

References 13 publications

Review Paper on Power Efficient Hybrid D-Flip Flop

Review Paper on Power Efficient Hybrid D-Flip Flop

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