Review Paper on Power Efficient Hybrid D-Flip Flop

Abstract

ABSTRACT:In nanometer CMOS technologies leakage powerhas become a serious concern and is a very important issue in hardware and software VLSI design. The leakage powerincreases as technology is scaled down. Low power flip-flops play a vital role for the design of low-power digital systems. In thispaper several different flip flop topologies are analyzed andpower efficient flip flop method is proposed. This paper presentssurvey on low power hybrid dual dynamic flip flop (DDFF) andembedded logic module (DDFF-ELM) based on DDFF. Thissurvey concludes that ultra low leakage CMOS structure calledas sleepy stack inverter pair method which is efficient in leakagepower reduction for design of low power hybrid flip flop thusproviding circuit designer with new choice to handle leakagepower problem.