Compact Modeling of Nanoscale Trapezoidal FinFETs

Fasarakis, N.; Karatsori, Theano A.; Tsormpatzoglou, A.; Tassis, D. H.; Papathanasiou, K.; Bucher, Matthias; Ghibaudo, G.; Dimitriadis, C. A.

doi:10.1109/ted.2013.2284503

Cited by 35 publications

(11 citation statements)

References 22 publications

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“…FinFET of triangular fin shape with 20 nm channel length is designed on Cogenda's GDS2Mesh 3D construction Technology Computer Aided Design (TCAD) tool [10]. The geometrical dimensions used in design are listed in Table 1.…”

Section: Device Design Parameters and Materials Compositionmentioning

confidence: 99%

Comparative Simulation Analysis of Process Parameter Variations in 20 nm Triangular FinFET

Shukla

Gill

Kaur

et al. 2017

Active and Passive Electronic Components

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Technology scaling below 22 nm has brought several detrimental effects such as increased short channel effects (SCEs) and leakage currents. In deep submicron technology further scaling in gate length and oxide thickness can be achieved by changing the device structure of MOSFET. For 10–30 nm channel length multigate MOSFETs have been considered as most promising devices and FinFETs are the leading multigate MOSFET devices. Process parameters can be varied to obtain the desired performance of the FinFET device. In this paper, evaluation of on-off current ratio (Ion/Ioff), subthreshold swing (SS) and Drain Induced Barrier Lowering (DIBL) for different process parameters, that is, doping concentration (1015/cm3 to 1018/cm3), oxide thickness (0.5 nm and 1 nm), and fin height (10 nm to 40 nm), has been presented for 20 nm triangular FinFET device. Density gradient model used in design simulation incorporates the considerable quantum effects and provides more practical environment for device simulation. Simulation result shows that fin shape has great impact on FinFET performance and triangular fin shape leads to reduction in leakage current and SCEs. Comparative analysis of simulation results has been investigated to observe the impact of process parameters on the performance of designed FinFET.

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Section: Device Design Parameters and Materials Compositionmentioning

confidence: 99%

Comparative Simulation Analysis of Process Parameter Variations in 20 nm Triangular FinFET

Shukla

Gill

Kaur

et al. 2017

Active and Passive Electronic Components

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“…The DIBL parameter is the horizontal displacement of the transfer characteristics at constant drain current, (W ef f /L g )× 10 −7 for drain voltage V d = 0.02V and 1V [17]. The simulated V-I characteristics of rectangular and trapezoidal TG FinFET have been shown in Fig.…”

Section: Rectangular and Trapezoidal Tg Bulk Finfets Structuresmentioning

confidence: 99%

Performance analysis of rectangular and trapezoidal TG bulk FinFETs for 20 nm gate length

Gaurav

Gilly

Kaurz

2015

2015 Annual IEEE India Conference (INDICON)

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FinFETs are the best alternatives or substitutes for the continuous downscaling of conventional MOSFETs. In this paper, the electrical performance of rectangular and trapezoidal TG bulk FinFETs for 20 nm gate length has been analyzed using 3D numerical device simulator. It was found that changing the fin shape from rectangular to trapezoidal leads to reduction in Short Channel Effects like leakage current, drain induced barrier lowering and subthreshold swing. The effects of change in equivalent fin width while moving from rectangular to trapezoidal fin shape on the device performance has also been studied.

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“…The quantum confinement generates no current conduction at the front interface, but at a distance x c from the front interface (9,10). For this reason, the value of x c can be calculated using equation [8], where A C and B C are model parameters:…”

Section: Device Characteristicsmentioning

confidence: 99%

“…Due to this effect the effective value of the silicon film thickness (t Si ) and front oxide thickness (t oxf ) are determined by the equations [9] and [10]: Applying the model in Dynamic Threshold mode By the V T x V GB curve calculated from the analytical model, it is possible to determine the value of V T of the UTBB operating in: DT, eDT and inverse-eDT modes.…”

Section: Device Characteristicsmentioning

confidence: 99%

Threshold Voltage Modeling for Dynamic Threshold UTBB SOI in Different Operation Modes

et al. 2015

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This paper presents an analytical model to determine the threshold voltage in Ultrathin Body and Buried Oxide Fully Depleted Silicon on Insulator (UTBB FD SOI) devices with Ground Plane (GP) implantation operating in three dynamic modes, simple Dynamic Threshold (DT), enhanced DT and inverse eDT mode. The analytical model is based on the Martino et al model adding the quantum confinement effect. The results show that the analytical model proposed has a good agreement to experimental data.

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Compact Modeling of Nanoscale Trapezoidal FinFETs

Cited by 35 publications

References 22 publications

Comparative Simulation Analysis of Process Parameter Variations in 20 nm Triangular FinFET

Comparative Simulation Analysis of Process Parameter Variations in 20 nm Triangular FinFET

Performance analysis of rectangular and trapezoidal TG bulk FinFETs for 20 nm gate length

Threshold Voltage Modeling for Dynamic Threshold UTBB SOI in Different Operation Modes

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