Compact model for short-channel symmetric double-gate junctionless transistors

Verilog-A implementation of a double-gate junctionless compact model for DC circuit simulations

“…Since it is not possible to get an analytic solution for the surface potential in (2), an iterative solution is showed in [18], where a precision better than 0.01% is obtained with a maximum of two iterations.…”

“…Also, expressions for functions SaN, Sb, SaP are defined in [18]. The final expression for the total drain current valid in both regimes is equal to:…”

“…where the effective mobility is given by the superposition of two parallel currents: one flowing through the center with a constant mobility m 0 and the other at the surface of the silicon layer, which presents scattering effects. As a result, surface mobility can be calculated as in [18]:…”

Semianalytical modeling of the depletion layers and their effects on the threshold voltage of a junctionless double‐gate MOSFET including trapped charges

“…Using the long‐channel approximation, analytical models including charge‐based potential, full range current model, variation of the threshold voltage caused by random dopant fluctuations, and technological constrains and design limitations have been investigated and developed for JL MOSFETs. Also, using the minimum central potential, the threshold voltage shift and the subthreshold slope for symmetric JL MOSFETs working in depletion and accumulation conditions have been determined and compared with the experimental results …”

“…Also, using the minimum central potential, the threshold voltage shift and the subthreshold slope for symmetric JL MOSFETs working in depletion and accumulation conditions have been determined and compared with the experimental results. 8,9 From the other point of view, some studies have investigated the effects of the fixed oxide charges at the Si-SiO 2 interface on the threshold voltage and other electrical properties of the JLDG MOSFETs. [10][11][12][13][14][15][16][17] Generally, there are 4 kinds of trapped charges at the Si-SiO 2 interface in the MOSFETs: (1) the fixed oxide charges that are due to structural defects (ionized silicon) in the oxide layer; (2) the mobile oxide charges that are caused by ionic impurities like Na + ; (3) the oxide trapped charges that are due to holes or electrons trapped in the bulk of the oxide by ionizing radiation, avalanche injection, tunneling, or other mechanisms; and (4) the interface trapped charges that are due to bond breaking processes like hot electrons in which the high electric field causes the impact ionization of the carriers and the generated hot electrons are injected into the Si-SiO 2 interface.…”