Compact FPGA implementation of Camellia

Yalla, Panasayya; Kaps, Jens-Peter

doi:10.1109/fpl.2009.5272349

Cited by 19 publications

(10 citation statements)

References 8 publications

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“…Also, it requires less clock cycles per round (17) compared to the implementation in [14] (it requires 35 clock cycles) and the implementation in [15] (it requires 49 clock cycles). Moreover, it achieves much better implementation efficiency (T/#S) compared to the 8-bit FPGA architectures of AES-128 and Camellia-128.…”

Section: Fpga Implementation and Resultsmentioning

confidence: 99%

8‐bit serialised architecture of SEED block cipher for constrained devices

Pirpilidis

Pyrgas

Kitsos

2020

IET Circuits, Devices & Systems

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This study presents an 8-bit serialised architecture of SEED block cipher for constrained devices. The circuit utilises 356 FPGA slices and 447 1-bit registers flip-flops (FFs) in the BASYS3 board, operates with an 8-bit datapath and is aimed for use on area constraints devices. In order to keep the usage of hardware resources to a minimum but, at the same time, achieve a high level of security, the key generation process of SEED is implemented through an on-the-fly procedure. In addition, the necessary S-boxes are implemented using composite field arithmetic without using any block RAMs, resulting in a very compact implementation. The proposed architecture achieves a maximum frequency equal to 125 MHz with a total latency of 280 clock cycles and a throughput up to 57.1 Mbps for encryption or decryption.

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Section: Fpga Implementation and Resultsmentioning

confidence: 99%

8‐bit serialised architecture of SEED block cipher for constrained devices

Pirpilidis

Pyrgas

Kitsos

2020

IET Circuits, Devices & Systems

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“…Table I shows the detailed results of our implementations of HIGHT and Present. We also included the implementation results of Camellia and TinyXTEA which were done by our group previously [11], [16]. The results for AES were obtained by using the VHDL code for the ASIC implementation reported in [17] and synthesizing it for our target FPGA.…”

Section: Implementation Resultsmentioning

confidence: 99%

“…However, some ciphers require intermediate data values. For example in the case of Camellia [11], multiple values from disparate locations are required to perform a single computation. This makes use of DRAM more appropriate.…”

Section: B Plaintext and Key Storagementioning

confidence: 99%

Lightweight Cryptography for FPGAs

Yalla

Kaps

2009

2009 International Conference on Reconfigurable Computing and FPGAs

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101

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Abstract-The advent of new low-power Field Programmable Gate Arrays (FPGA) for battery powered devices opens a host of new applications to FPGAs. In order to provide security on resource constrained devices lightweight cryptographic algorithms have been developed. However, there has not been much research on porting these algorithms to FPGAs. In this paper we propose lightweight cryptography for FPGAs by introducing block cipher independent optimization techniques for Xilinx Spartan3 FPGAs and applying them to the lightweight cryptographic algorithms HIGHT and Present. Our implementations are the first reported of these block ciphers on FPGAs. Furthermore, they are the smallest block cipher implementations on FPGAs using only 117 and 91 slices respectively, which makes them comparable in size to stream cipher implementations. Both are less than half the size of the AES implementation by Chodowiec and Gaj without using block RAMs. Present's throughput over area ratio of 240 Kbps/slice is similar to that of AES, however, HIGHT outperforms them by far with 720 Kbps/slice.

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“…In [17], involutive ciphers ICEBERG has been proposed specifically for FPGA implementation. There are also few compact implementations on FPGAs of some well known traditional block ciphers, like AES [22,32,40], Serpent [1], Camellia [30] and Misty [29]. These implementations generally use some special techniques for serialization to occupy less slices on FPGAs.…”

Section: Related Workmentioning

confidence: 99%

Khudra: A New Lightweight Block Cipher for FPGAs

Kolay

Mukhopadhyay

2014

Security, Privacy, and Applied Cryptography Engineering

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Abstract. The paper shows that designing lightweight block ciphers for the increasingly popular Field Programmable Gate Arrays (FPGAs) needs a new revisit. It shows that due to the underlying FPGA architecture many popular techniques for lightweight block ciphers which work on Application Specific Integrated Circuits (ASICs) does not apply to FPGAs. The paper identifies new methods and design criteria for lightweight block ciphers operating on FPGAs. Using these guidelines, a new block cipher Khudra based on the recursive Feistel structure is designed, which has a 64 bit block size and 80 bits of key. Rigorous cryptanalysis, ranging from linear and differential cryptanalysis to more powerful attacks like impossible differential, related key attacks etc. have been performed to justify that 18 rounds of Khudra provide sufficient security margin. Finally, the cipher has been implemented in two different flavors, Khudra-I and Khudra-II, on low cost FPGAs like Xilinx Spartan-III XC3S400 and extensively compared with other contemporary ciphers like PRESENT, Piccolo and compact implementations of other standard cipher like AES, Camellia etc. The implementation results show that Khudra requires at least around 45% less slices and 29% less AT product compared to round wise implementation of any of the contemporary lightweight block cipher.

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Compact FPGA implementation of Camellia

Cited by 19 publications

References 8 publications

8‐bit serialised architecture of SEED block cipher for constrained devices

8‐bit serialised architecture of SEED block cipher for constrained devices

Lightweight Cryptography for FPGAs

Khudra: A New Lightweight Block Cipher for FPGAs

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