8‐bit serialised architecture of SEED block cipher for constrained devices

Pirpilidis, Filippos; Pyrgas, Lampros; Kitsos, Paris

doi:10.1049/iet-cds.2018.5354

Cited by 5 publications

(2 citation statements)

References 19 publications

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“…For example, the RSA has a complex design and low-level efficiency, and hence it is not appropriate for low-area applications [37]. Nowadays, some of the block ciphers from the symmetric algorithms are also used for the data security purpose and examples of the block cipher are SIMON [38], SEED [39], KLEIN [40], HIGHT [41], KASUMI [42], CLEFIA [43], PRESENT [44,45], etc. These low complexity light weight block ciphers can be used in wireless communications (i.e., internet of things (IoT) applications).…”

Section: Introductionmentioning

confidence: 99%

A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application

Kumar

Reddy²,

Rinaldi

et al. 2021

Electronics

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Nowadays, a huge amount of digital data is frequently changed among different embedded devices over wireless communication technologies. Data security is considered an important parameter for avoiding information loss and preventing cyber-crimes. This research article details the low power high-speed hardware architectures for the efficient field programmable gate array (FPGA) implementation of the advanced encryption standard (AES) algorithm to provide data security. This work does not depend on the look up tables (LUTs) for the implementation the SubBytes and InvSubBytes stages of transformations of the AES encryption and decryption; this new architecture uses combinational logical circuits for implementing SubBytes and InvSubBytes transformation. Due to the elimination of LUTs, unwanted delays are eliminated in this architecture and a subpipelining structure is introduced for improving the speed of the AES algorithm. Here, modified positive polarity reed muller (MPPRM) architecture is inserted to reduce the total hardware requirements, and comparisons are made with different implementations. With MPPRM architecture introduced in SubBytes stages, an efficient mixcolumn and invmixcolumn architecture that is suited to subpipelined round units is added. The performances of the proposed AES-MPPRM architecture is analyzed in terms of number of slice registers, flip flops, number of slice LUTs, number of logical elements, slices, bonded IOB, operating frequency and delay. There are five different AES architectures including LAES, AES-CTR, AES-CFA, AES-BSRD, and AES-EMCBE. The LUT of the AES-MPPRM architecture designed in the Spartan 6 is reduced up to 15.45% when compared to the AES-BSRD.

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Section: Introductionmentioning

confidence: 99%

A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application

Kumar

Reddy²,

Rinaldi

et al. 2021

Electronics

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“…However, the lightweight cipher affects the performance when the system has a huge number of devices during the communication [24]. Additionally, the lightweight block ciphers offer only a lower level of security than the conventional algorithms [25]. Authentication, confidentiality, and integrity are considered as the significant objectives of the cryptographic protocols.…”

Section: Introductionmentioning

confidence: 99%

Implementation of Speed-Efficient Key-Scheduling Process of AES for Secure Storage and Transmission of Data

Kumar

Balmuri²,

Marchewka

et al. 2021

Sensors

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Nowadays, a large number of digital data are transmitted worldwide using wireless communications. Therefore, data security is a significant task in communication to prevent cybercrimes and avoid information loss. The Advanced Encryption Standard (AES) is a highly efficient secure mechanism that outperforms other symmetric key cryptographic algorithms using message secrecy. However, AES is efficient in terms of software and hardware implementation, and numerous modifications are done in the conventional AES architecture to improve the performance. This research article proposes a significant modification to the AES architecture’s key expansion section to increase the speed of producing subkeys. The fork–join model of key expansion (FJMKE) architecture is developed to improve the speed of the subkey generation process, whereas the hardware resources of AES are minimized by avoiding the frequent computation of secret keys. The AES-FJMKE architecture generates all of the required subkeys in less than half the time required by the conventional architecture. The proposed AES-FJMKE architecture is designed and simulated using the Xilinx ISE 5.1 software. The Field Programmable Gate Arrays (FPGAs) behaviour of the AES-FJMKE architecture is analysed by means of performance count for hardware resources, delay, and operating frequency. The existing AES architectures such as typical AES, AES-PNSG, AES-AT, AES-BE, ISAES, AES-RS, and AES-MPPRM are used to evaluate the efficiency of AES-FJMKE. The AES-FJMKE implemented using Spartan 6 FPGA used fewer slices (i.e., 76) than the AES-RS.

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Ultra-lightweight FPGA-based RC5 designs via data-dependent rotation block optimization

Birgani

Timarchi

Khalid

2022

Microprocessors and Microsystems

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8‐bit serialised architecture of SEED block cipher for constrained devices

Cited by 5 publications

References 19 publications

A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application

A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application

Implementation of Speed-Efficient Key-Scheduling Process of AES for Secure Storage and Transmission of Data

Ultra-lightweight FPGA-based RC5 designs via data-dependent rotation block optimization

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