CMOS planar spiral inductor modeling and low noise amplifier design

Telli, Ali; Demır, Şımşek; Askar, M.

doi:10.1016/j.mejo.2005.06.019

Cited by 4 publications

(4 citation statements)

References 13 publications

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“…The current shared cascode amplifier provides a low-power characteristic under the low voltage supply. Because 1 and 2 share the same bias current, the total power consumption is minimized [6,12,16]. For a cascode amplifier, the overall noise figure can be obtained in terms of the noise figure (NF) and gain of each stage as follows:…”

Section: Low-voltage Widebandmentioning

confidence: 99%

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A Low-Power Ultrawideband Low-Noise Amplifier in 0.18 μm CMOS Technology

Chen¹

2013

Active and Passive Electronic Components

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This paper presents an ultrawideband low-noise amplifier chip using TSMC 0.18 m CMOS technology. We propose a UWB low noise amplifier (LNA) for low-voltage and low-power application. The present UWB LNA leads to a better performance in terms of isolation, chip size, and power consumption for low supply voltage. This UWB LNA is designed based on a current-reused topology, and a simplified RLC circuit is used to achieve the input broadband matching. Output impedance introduces the LC matching method to reduce power consumption. The measured results of the proposed LNA show an average power gain (S 21) of 9 dB with the 3 dB band from 3 to 5.6 GHz. The input reflection coefficient (S 11) less than −9 dB is from 3 to 11 GHz. The output reflection coefficient (S 22) less than −8 dB is from 3 to 7.5 GHz. The noise figure 4.6-5.3 dB is from 3 to 5.6 GHz. Input third-orderintercept point (IIP 3) of 2 dBm is at 5.3 GHz. The dc power consumption of this LNA is 9 mW under the supply of a 1 V supply voltage. The chip size of the CMOS UWB LNA is 1.03 × 0.78 mm 2 in total.

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Section: Low-voltage Widebandmentioning

confidence: 99%

“…The cascode LNA design is full of trade-offs between optimal gain, low noise figure, input and output matching, linearity, and power consumption. Moreover, to avoid oscillation, the parasitic couplings have to be minimized [16]. The sizes of the devices of the LNA are shown in Table 1.…”

Section: Low-voltage Widebandmentioning

confidence: 99%

A Low-Power Ultrawideband Low-Noise Amplifier in 0.18 μm CMOS Technology

Chen¹

2013

Active and Passive Electronic Components

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“…Additional requirement to the LNA is the low power consumption, which is especially important in portable communications systems [1]. Various techniques to improve the LNA performances were proposed [2][3][4][5].…”

Section: Introductionmentioning

confidence: 99%

On-Chip Inductor Technique for Improving LNA Performance Operating at 15 GHz

Hasaneen¹,

Okely²

2012

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This paper presents a technique for low noise figure reduction of low-noise amplifier (LNA). The proposed LNA is designed in a source degeneration technique that offers lower noise figure. The resistance of the on-chip inductor is reduced by using multilayer that significantly reduces the thermal noise due to spiral inductor. Also, using spiral inductor as a gate inductor reduces the effect of the input parasitic capacitance on the noise figure and provides a good matching at the input and output of the LNA. The results of the LNA using multilayer on-chip inductor compared will off-chip inductor have been illustrated. It shows that the proposed technique reduces significantly the noise figure and improves the matching. The proposed LNA is designed in 0.13 μm process with 1.3 V supply voltage and simulated using Advanced Design System (ADS) software. The simulation results show that the LNA is unconditionally stable and provides a forward gain of 11.087 dB at operating frequency of 15 GHz with 1.784 dB noise figure and input and output impedance matching of -17.93 dB, and -10.04 dB.

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“…From both figure we can also see that the performance between the circuits have a bigger difference at higher frequency. This is because at high frequency operation the parasitic effects in the circuit are increased [3]. Comparison input and output return loss performance is given in Fig.…”

Section: Introductionmentioning

confidence: 99%

Parasitic effects of spiral inductors on the performance of GaAs-based MMIC low noise amplifier

Norhapizin

Ismail

Ismat

et al. 2008

2008 IEEE International Conference on Semiconductor Electronics

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This paper is discusses about parasitic effect of spiral inductors on 5.8 GHz low noise amplifier (LNA) performances based on 0.5 µm GaAs pHEMT technology. Using S-parameter simulation, performance of the LNA between lump and distributed circuit are compared at 5.8 GHz. Electrical performance of the LNA performances by placing ideal components with non-ideal components shows that noise figure is increased by 2.31 dB, gain is decreased by 11.38 dB and input and output return loss is increased by 0.31 dB and 4.31 dB respectively. By using non-ideal components in the lump circuit analysis, it is shown that the spiral inductor has a noticeable impact on the LNA performance. The parasitic effects including self resonance on spiral inductors is discussed. This analysis is essential to ensure the simulation results yield realistic measured results for the fabricated LNA. Therefore the designer will have a good estimation on the performance of the LNA performance during the design stage prior to the testing stage.

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CMOS planar spiral inductor modeling and low noise amplifier design

Cited by 4 publications

References 13 publications

A Low-Power Ultrawideband Low-Noise Amplifier in 0.18 μm CMOS Technology

A Low-Power Ultrawideband Low-Noise Amplifier in 0.18 μm CMOS Technology

On-Chip Inductor Technique for Improving LNA Performance Operating at 15 GHz

Parasitic effects of spiral inductors on the performance of GaAs-based MMIC low noise amplifier

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