CMOS integration of dual work function phase controlled Ni FUSI with simultaneous silicidation of NMOS (NiSi) and PMOS (Ni-rich silicide) gates on HfSiON

Lauwers, A.; Veloso, A.; Hoffmann, T.; Dal, M.J.H. van; Vrancken, C.; Brus, S.; Locorotondo, S.; Marneffe, J.-F. de; Sijmus, B.; Kubicek, S.; Chiarella, T.; Pawlak, Małgorzata; Opsomer, Karl; Niwa, Miki; Mitsuhashi, R.; Anil, K.G.; Yu, Hao; Demeurisse, C.; Verbeeck, R.; Potter, M. de; Absil, Philip; Maex, Karen; Jurczak, M.; Biesemans, S.; Kittl, Jorge

doi:10.1109/iedm.2005.1609433

Cited by 21 publications

(13 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…2, should be realized. [19][20][21] For fabricating the poly-Si and metal stacked gate structure, poly-Si patterns with fine sidewalls are constructed by applying high-potential RIE and isotropic plasma etching technologies with highly accurate dimensions and controlled profiles.…”

Section: Feol-and Beol-related Plasma Etching Technologymentioning

confidence: 99%

Developments of Plasma Etching Technology for Fabricating Semiconductor Devices

Abe¹,

Yoneda

Fujiwara

2008

jjap

279

163

View full text Add to dashboard Cite

Plasma etching technologies such as reactive ion etching (RIE), isotropic etching, and ashing/plasma cleaning are the currently used booster technologies for manufacturing all silicon devices based on the scaling law. The needs-driven conversion from the wet etching process to the plasma/dry etching process is reviewed. The progress made in plasma etching technologies is described from the viewpoint of requirements for the manufacturing of devices. The critical applications of RIE, isotropic etching, and plasma ashing/cleaning to form precisely controlled profiles of high-aspect-ratio contacts (HARC), gate stacks, and shallow trench isolation (STI) in the front end of line (FEOL), and also to form precise via holes and trenches used in reliable Cu/low-k (low-dielectric-constant material) interconnects in the back end of line (BEOL) are described in detail. Some critical issues inherent to RIE processing, such as the RIE-lag effect, the notch phenomenon, and plasma-induced damage including charge-up damage are described. The basic reaction mechanisms of RIE and isotropic etching are discussed. Also, a procedure for designing the etching process, which is strongly dependent on the plasma reactor configuration, is proposed. For the more precise critical dimension (CD) control of the gate pattern for leading-edge devices, the advanced process control (APC) system is shown to be effective.

show abstract

Section: Feol-and Beol-related Plasma Etching Technologymentioning

confidence: 99%

Developments of Plasma Etching Technology for Fabricating Semiconductor Devices

Abe¹,

Yoneda

Fujiwara

2008

jjap

279

163

View full text Add to dashboard Cite

show abstract

“…In this letter, we propose a cost efficient method that achieves a dual dielectric (by means of Al and Yb implantation and anneal), and dual metal gate (by means of poly-Si etchback silicide phase engineering [15]), CMOS flow, without any dual deposition. This method achieves a total WF range of ∼700 meV.…”

Section: Cost-effective Low V T Ni-fusi Cmos Onmentioning

confidence: 99%

Cost-Effective Low $V_{t}$ Ni-FUSI CMOS on SiON by Means of Al Implant (pMOS) and $\hbox{Yb}{+}\hbox{P}$ Coimplant (nMOS)

Lauwers

Veloso

Chang

et al. 2008

IEEE Electron Device Lett.

Self Cite

View full text Add to dashboard Cite

Low V t Ni fully silicided (FUSI) devices are demonstrated making use of Al implantation for pMOS and Yb or Yb+P implantation for nMOS combined with Ni-silicide phase engineering. When Yb(+P) and Al implantation are followed by a high temperature anneal, significant segregation of Yb or Al toward the Ni-FUSI/SiON interface is observed and large V t shifts of 450 mV (330 mV) and 200 mV are obtained for nMOS NiSi FUSI/SiON devices and pMOS Ni-rich FUSI/SiON devices, respectively, as compared to the undoped reference devices. The V t shifts are preserved down to the shortest gate lengths. For both Al and Yb, the V t shifts are explained by the dopants reacting with and modifying the dielectric. Thus, the low V t dual implantation approach proposed achieves a low-cost "dual dielectric" implementation without the need of dual deposition of dielectrics or capping layers. In the case of Yb implantation followed by a high temperature anneal, a significant reduction in the inversion dielectric thickness is observed, indicating that the reaction between Yb and SiON results in the formation of a high-κ dielectric. The Yb diffusion and reaction at the interface can be engineered using a P coimplant.

show abstract

“…To meet the work-function (WF) requirements for Ni-FUSI electrode, numerous approaches have been studied, such as by the impurity doping technologies (P, As, B, Al, etc.) [4], [5], by controlling the Ni silicide phase formation (i.e., Ni-rich silicide versus Ni monosilicide) [6], or by using Ni-based alloys (such as Ni-Yb, Ni-Tb, and Ni-Pt) for FUSI formation [1], [7]. Despite of these efforts, low V t n-MOSFETs using Ni-FUSI electrode is still not readily viable for high-performance applications.…”

Section: Introductionmentioning

confidence: 99%

Demonstration of Low $V_{t}$ Ni-FUSI N-MOSFETs With SiON Dielectrics by Using a $\hbox{Dy}_{2}\hbox{O}_{3}$ Cap Layer

Hónɡ

Chang

Veloso

et al. 2007

IEEE Electron Device Lett.

Self Cite

View full text Add to dashboard Cite

This letter reports a novel approach to achieve low threshold voltage (V t ) Ni-FUlly-SIlicide (FUSI) nMOSFETs with SiON dielectrics. By using a Dysprosium-oxide (Dy 2 O 3 ) cap layer with a thickness of 5 Å on top of the SiON host dielectrics, V t,lin of 0.18 V for long-channel devices (L g = 1 µm) using NiSi-FUSI electrode is obtained, satisfying the high-performance device requirements. The V t modulation due to the Dy 2 O 3 cap layer is also maintained in the short-channel devices (with an L g,min of 90 nm as demonstrated in this letter). In particular, approximately 150× reduction in gate leakage current is seen while preserving the dielectric capacitance equivalent thickness after adding the Dy 2 O 3 cap layer on SiON dielectrics, likely due to a high-κ layer (DySiON) formation during device source/drain activation process. We also report that the Dy 2 O 3 layer does not vitally degrade the device reliability, such as positive-bias temperature instability and time-dependant dielectrics breakdown.Index Terms-Dysprosium-oxide (Dy 2 O 3 ) cap layer, low V t nMOSFETs, Ni-FUlly-SIlicide (FUSI), SiON.

show abstract

CMOS integration of dual work function phase controlled Ni FUSI with simultaneous silicidation of NMOS (NiSi) and PMOS (Ni-rich silicide) gates on HfSiON

Cited by 21 publications

References 0 publications

Developments of Plasma Etching Technology for Fabricating Semiconductor Devices

Developments of Plasma Etching Technology for Fabricating Semiconductor Devices

Cost-Effective Low $V_{t}$ Ni-FUSI CMOS on SiON by Means of Al Implant (pMOS) and $\hbox{Yb}{+}\hbox{P}$ Coimplant (nMOS)

Demonstration of Low $V_{t}$ Ni-FUSI N-MOSFETs With SiON Dielectrics by Using a $\hbox{Dy}_{2}\hbox{O}_{3}$ Cap Layer

Contact Info

Product

Resources

About