2007
DOI: 10.1016/j.mee.2007.04.072
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CMOS gate oxide defects induced by pre-gate plasma process

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Cited by 5 publications
(2 citation statements)
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“…Indeed, a reactive ion etching process enables a better etching dimensions control, due to very high anisotropy compared with usually isotropic wet etching conditions. Nonetheless, wet patterning with photosensitive resist is still the reference process when either sensitive materials (namely gate oxides [1]) are used or when dimensions are relaxed. This paper deals with the resist protection integrity during the whole wet etching.…”
Section: Introductionmentioning
confidence: 99%
“…Indeed, a reactive ion etching process enables a better etching dimensions control, due to very high anisotropy compared with usually isotropic wet etching conditions. Nonetheless, wet patterning with photosensitive resist is still the reference process when either sensitive materials (namely gate oxides [1]) are used or when dimensions are relaxed. This paper deals with the resist protection integrity during the whole wet etching.…”
Section: Introductionmentioning
confidence: 99%
“…Gate oxides areas are still nowadays defined thanks to a combination of a photo lithography and a wet etch. Indeed this latter is preferred to plasma etching to avoid any transistor channel roughness and reliability degradation [1]. During this soft mask patterning, the gate oxide under the resist can be degraded by two different mechanisms: either a lateral wet etchant infiltration at the PR(Photo resist) / gate oxide interface [2], or a vertical diffusion of chemicals down to this same interface.…”
Section: Introductionmentioning
confidence: 99%