Articles you may be interested in X-ray photoelectron spectroscopy analysis of the effect of temperature upon surface composition of InP etched in Cl2-based inductively coupled plasma

Articles you may be interested inDevelopment of plasma etching processes to pattern sub-15 nm features with PS-b-PMMA block copolymer masks: Application to advanced CMOS technology J. Vac. Sci. Technol. B 32, 051806 (2014); 10.1116/1.4895334 Patterning of silicon nitride for CMOS gate spacer technology. I. Mechanisms involved in the silicon consumption in CH3F/O2/He high density plasmas Design of notched gate processes in high density plasmas Germanium etching in high density plasmas for 0.18 μm complementary metal-oxide-semiconductor gate patterning applicationsGate structures with dimensions smaller than 0.1 m on gate oxides thinner than 2 nm have been patterned in a high density plasma helicon source. The chemistry which seems best adapted uses an HBr/O 2 mixture ensuring high selectivity to the gate oxide and an etch anisotropy allowing the critical dimension control in the 0.1 m regime to be acceptable. Kinetic ellipsometry has been used to measure silicon and SiO 2 etch rates and carefully control the process in real time. X-ray photoelectron spectroscopy ͑XPS͒ studies have been performed to determine the chemical topography of SiO 2 masked gate stacks with different aspect ratios. In particular, the chemical composition and thickness of the sidewall passivation layer have been determined. We have also observed an unsuspected behavior of thin gate oxides during the overetch step of the process. By combining XPS and spectroscopic ellipsometry, we have attributed this behavior to reactive species penetration through the thin gate oxide. This phenomenon could play an important role in the sub 0.1 m complementary metal-oxide-semiconductors process optimization.

We have evidenced an unexpected behavior of thin gate oxide layers (thickness in the range 2–4 nm) exposed to plasma processes developed for the patterning of 0.1 μm silicon gates. During the low-energy overetch step of the process, an oxidation of the bulk underlying silicon takes place, leading to the growth of the gate oxide layer. Experimental results obtained from in situ kinetic and spectroscopic ellipsometry measurements and supported by x-ray photoelectron spectroscopy analyses are presented to highlight this phenomenon.

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