CMOS-embedded STT-MRAM arrays in 2x nm nodes for GP-MCU applications

Shum, D.; Houssameddine, D.; Woo, S. T.; You, Yuan; Wong, J.; Wong, K. W.; Wang, C. C.; Lee, K. H.; Yamane, K.; Naik, V. B.; Seet, C. S.; Tahmasebi, T.; Chen, Hai; Yang, Han-Chul; Thiyagarajah, Naganivetha; Ren, Chao; Ting, J. W.; Chung, N. L.; Ling, T.; Chan, T. H.; Siah, S. Y.; Nair, Rajesh V.; Deshpande, S.; Whig, R.; Nagel, K.; Aggarwal, S.; DeHerrera, M.; Janesky, J.; Lin, Mingjie; Chia, Hao-Chung; Hossain, Moinul; Lu, Hao; Ikegawa, S.; Mancoff, F. B.; Shimon, G.; Slaughter, J. M.; Sun, J. J.; Tran, Michaël; Alam, Syed Q.; Andre, T.

doi:10.23919/vlsit.2017.7998174

Cited by 35 publications

(16 citation statements)

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“… When it comes to implementing the above as memory arrays, such arrays are currently focused on crossbar array architectures that typically make use of either phase-change materials (see [ 173 , 174 ]) or resistive materials (see [ 43 ], [ 175 , 176 , 177 ]). More work is still needed on realizing memory arrays using either FeRAM or MRAM, though there have already been some successes in constructing STT-MRAM memory arrays [ 178 ], and there have also been some notable moves in this direction using SOT-MRAM lately [ 179 ]. By and large, this paper has focused on discussing single device implementations and how they might be used for logic operations, but constructing larger-scale non-volatile memory arrays has also been given substantial treatment in the literature and significant progress has been made [ 180 , 181 ].…”

Section: Discussionmentioning

confidence: 99%

In-Memory Logic Operations and Neuromorphic Computing in Non-Volatile Random Access Memory

Xiong

et al. 2020

Materials

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Recent progress in the development of artificial intelligence technologies, aided by deep learning algorithms, has led to an unprecedented revolution in neuromorphic circuits, bringing us ever closer to brain-like computers. However, the vast majority of advanced algorithms still have to run on conventional computers. Thus, their capacities are limited by what is known as the von-Neumann bottleneck, where the central processing unit for data computation and the main memory for data storage are separated. Emerging forms of non-volatile random access memory, such as ferroelectric random access memory, phase-change random access memory, magnetic random access memory, and resistive random access memory, are widely considered to offer the best prospect of circumventing the von-Neumann bottleneck. This is due to their ability to merge storage and computational operations, such as Boolean logic. This paper reviews the most common kinds of non-volatile random access memory and their physical principles, together with their relative pros and cons when compared with conventional CMOS-based circuits (Complementary Metal Oxide Semiconductor). Their potential application to Boolean logic computation is then considered in terms of their working mechanism, circuit design and performance metrics. The paper concludes by envisaging the prospects offered by non-volatile devices for future brain-inspired and neuromorphic computation.

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Section: Discussionmentioning

confidence: 99%

In-Memory Logic Operations and Neuromorphic Computing in Non-Volatile Random Access Memory

Xiong

et al. 2020

Materials

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“…To guarantee a high-quality test solution and improve the manufacturing process itself so as to improve yield, understanding all potential defects is of great importance. The STT-MRAM manufacturing process mainly consists of the standard CMOS fabrication steps and the integration of MTJ devices into metal layers (e.g., between M4 and M5 layers [29,30]). Fig.…”

Section: Defect Space and Classificationmentioning

confidence: 99%

Defect and Fault Modeling Framework for STT-MRAM Testing

Rao

Taouil

et al. 2021

IEEE Trans. Emerg. Topics Comput.

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STT-MRAM mass production is around the corner as major foundries worldwide invest heavily on its commercialization. To ensure high-quality STT-MRAM products, effective yet cost-efficient test solutions are of great importance. This paper presents a systematic device-aware defect and fault modeling framework for STT-MRAM to derive accurate fault models which reflect the physical defects appropriately, and thereafter optimal and high-quality test solutions. An overview and classification of manufacturing defects in STT-MRAMs are provided with an emphasis on those related to the fabrication of magnetic tunnel junction (MTJ) devices, i.e., the data-storing elements. Defects in MTJ devices need to be modeled by adjusting the affected technology parameters and subsequent electrical parameters to fully capture the defect impact on both the device's electrical and magnetic properties, whereas defects in interconnects can be modeled as linear resistors. In addition, a complete single-cell fault space and nomenclature are defined, and a systematic fault analysis methodology is proposed. To demonstrate the use of the proposed framework, resistive defects in interconnect and pinhole defects in MTJ devices are analyzed for a single 1T-1MTJ memory cell. Test solutions for detecting these defects are also discussed.

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“…Among the various emerging memory technology described in Sect. 5.1, STT-MRAM is attracting a strong interest as storage-class memory (SCM) [5,10], DRAM replacement [11], and embedded nonvolatile memory [12], due to its fast switching, non-volatility, high endurance, CMOS compatibility and low current operation [13]. In addition, STT-RAM and spintronic devices in general can be implemented in novel non-von Neumann concepts of computing, e.g., as electronic synapse in neural networks [14], nonvolatile logic [15], and random number generator (RNG) [16].…”

Section: Spin-transfer Torque Magnetic Memory (Stt-mram)mentioning

confidence: 99%

Characterization and Modeling of Spin-Transfer Torque (STT) Magnetic Memory for Computing Applications

Carboni

2021

Special Topics in Information Technology

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With the ubiquitous diffusion of mobile computing and Internet of Things (IoT), the amount of data exchanged and processed over the internet is increasing every day, demanding secure data communication/storage and new computing primitives. Although computing systems based on microelectronics steadily improved over the past 50 years thanks to the aggressive technological scaling, their improvement is now hindered by excessive power consumption and inherent performance limitation associated to the conventional computer architecture (von Neumann bottleneck). In this scenario, emerging memory technologies are gaining interest thanks to their non-volatility and low power/fast operation. In this chapter, experimental characterization and modeling of spin-transfer torque magnetic memory (STT-MRAM) are presented, with particular focus on cycling endurance and switching variability, which both present a challenge towards STT-based memory applications. Then, the switching variability in STT-MRAM is exploited for hardware security and computing primitives, such as true-random number generator (TRNG) and stochastic spiking neuron for neuromorphic and stochastic computing.

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CMOS-embedded STT-MRAM arrays in 2x nm nodes for GP-MCU applications

Cited by 35 publications

References 0 publications

In-Memory Logic Operations and Neuromorphic Computing in Non-Volatile Random Access Memory

In-Memory Logic Operations and Neuromorphic Computing in Non-Volatile Random Access Memory

Defect and Fault Modeling Framework for STT-MRAM Testing

Characterization and Modeling of Spin-Transfer Torque (STT) Magnetic Memory for Computing Applications

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