Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance

Abstract

Abstract-Closed-form expressions of the resistance, capacitance, and inductance for interplane 3-D vias are presented in this paper. The closed-form expressions account for the 3-D via length, diameter, dielectric thickness, and spacing to ground. A 3-D numerical simulation is used to extract electromagnetic solutions of the resistance, capacitance, and inductance for comparison with the closed-form expressions, revealing good agreement between simulation and the physical models. The maximum error for the resistance, capacitance, and inductance is less than 8%.

Extreme ultraviolet lithography and three dimensional integrated circuit—A review

“…[95][96][97] The equivalent TSV self-capacitance is an important parameter for RC delay, which needs to be considered during TSV design. The equivalent TSV inductance is also important for interconnect performance such as SSN that is determined by TSV length.…”

A Distributed Filter Within a Switching Converter for Application to 3-D Integrated Circuits

“…This filter is described in this section. The resistance, inductance, and capacitance per unit length of the interconnects (Metal 3) and 3-D vias are extracted based on the predictive technology model (PTM) [23]- [25], as listed in Table I. The width of the interconnects is determined by the maximum current density of the MITLL 3-D technology.…”

Robust signaling techniques for through silicon via bundles

“…In [22], Friedman et al have developed the closed form expressions for a 3D via. Closed form expressions for R, L and C developed in [22] are for a single 3D via.…”

“…In [22], Friedman et al have developed the closed form expressions for a 3D via. Closed form expressions for R, L and C developed in [22] are for a single 3D via. Though these expressions cannot be used directly for a group of TSVs, it provides a good model to understand the electrical behavior of Through Silicon Vias.…”

“…The authors in [22] mentioned that the capacitance formula mentioned above gives a simple expression for hand calculation. However they mention that the capacitance is over-estimated using the above mentioned formula as it assumes that the electric field lines from 3D via terminate on the cylinder surrounding the via dielectric liner [22]. From Figure 4.20 it can be observed that as the TSV radius increases, the data rate of signaling techniques decreases.…”